This article introduces a digital conversion and linearization unit (DCLU) that performs signal conversion and power amplifier (PA) linearization when the digital-to-analog converter (DAC) is constrained by limited bit resolution. The proposed structure applies an error-and-distortion-feedback (EDF) processing principle that integrates re-quantization, noise shaping, and digital predistortion (DPD) within a single digital unit and avoids explicit inverse modeling. The embedded PA forward description uses a polar look-up table (PLUT) representation of the PA static AM/AM and AM/PM characteristics and a linear filter that captures the measured dynamic response. More advanced approaches are also described in terms of incorporating more elaborate forward models within the DCLU, together with a parallel multi-channel realization that relaxes internal clock-rate requirements through time-interleaved processing. The concept is validated through two RF measurement experiments using a 5G New Radio (NR) transmit waveform at 3.5 GHz and 3.6 GHz (NR band n78). The first experiment uses a broadband Gallium-Nitride (GaN) HMC1114 PA to demonstrate the proof of concept and quantify system behavior under reduced bit resolutions. The second experiment uses the Qorvo QPA3503 GaN Doherty PA to evaluate the approach for an amplifier type that is typically more challenging to linearize. The measured results show that the proposed approach maintains good linearization capability under reduced bit resolutions and, in the reported cases, provides improved transmit waveform quality relative to conventional reference DPD schemes, particularly at lower bit widths.

In this article, we propose a new robust and highly efficient digital predistortion (DPD) concept for the linearization of wideband RF power amplifiers (PAs). The proposed approach is based on the combination of a parallelized delta-sigma modulator (DSM) and a forward model of the PA. This concept applies multi-rate techniques on a DSM that incorporates the forward PA model in its feedback loop to perform the required signal predistortion. Such a technique eliminates the need of reverse modeling and its associated problems. The multi-rate approach relaxes enormously the clock speed requirement of the DPD, which allows handling high signal bandwidths at feasible sampling rates. Moreover, enhanced performance can be achieved without the need of increasing the order of the modulator which reduces the sensitivity of the system to gain variations and phase distortions caused by the nonlinear PA characteristics. Three time-interleaved parallel DPD (P-DPD) variants are described and introduced, all of them have been shown to offer increased accuracy, and consequently better linearization performance compared to the DSM-based DPD state-of-the-art. The proposed architectures are tested and assessed using extensive real-world RF measurements at the 3.6 GHz band utilizing wideband 100 MHz 5G New Radio (NR) transmit waveforms, evidencing excellent transmit signal quality.

This article presents two novel digital predistortion (DPD) based architectures that jointly mitigate the inphase/quadrature (IQ) modulator impairments and the power amplifier (PA) nonlinear distortion in wireless transmitters. The proposed architectures are multibit cartesian and complex delta-sigma modulator-based joint DPDs, called CDSM-JDPD and CXDSM-JDPD, respectively, which enable using low-cost digital-to-analog converters (DACs) while offering versatile linearization capabilities to combat the coexisting distortions of the PA and the IQ modulator. The proposed approach alleviates the need for reverse modeling and implementation of extra hardware to separately deal with frequency-dependent IQ impairments. Moreover, the CXDSM-JDPD enhances the linearization performance and relaxes the high oversampling ratio (OSR) requirement by quantizing the signal more efficiently. Furthermore, the presented concepts inherently support the use of low-resolution DACs, which offers a tremendous advantage in designing and implementing low-cost and energy-efficient radio transmitters. Extensive set of hardware-in-the-loop RF verification measurements with a commercial PA are provided, including two timely 5G New Radio (NR) scenarios at NR bands n3 and n78, while covering channel bandwidths up to 100 MHz and varying the OSR and the DAC bit resolution. The obtained results demonstrate the excellent linearization capabilities of the proposed solutions and their superiority compared to other DSM-based DPD approaches.