Storage swapping has been a critical technique used to relieve memory pressure and improve user experience. However, it generates lots of data writes in flash storage, deteriorating the lifetime and performance. In this paper, inspired by empirical studies on swap data access characteristics, we propose a novel data invalidation scheme, namely DISS, which includes two methods. First, a cross-layer swap-data invalidation method is proposed to invalidate swapped-in data at a low cost. Second, a swap data separation method is proposed to schedule swap data and file-backed data into different places. Experimental results show that DISS achieves encouraging flash lifetime and performance optimization.

Considering the potential benefits to lifespan and performance, zoned flash storage is expected to be incorporated into the next generation of consumer devices. However, due to the limited volatile cache and heterogeneous flash cells of consumer-grade flash storage, adopting a zone abstraction requires additional internal hardware design to maximize its benefits. To understand and efficiently improve the hardware design on consumer-grade zoned flash storage, we present ConZone—the first emulator tailored to the characteristics of consumer-grade zoned flash storage. Users can explore the internal architecture and management strategies of consumer-grade zoned flash storage and integrate the optimization with software. We validate the accuracy of ConZone by realizing a hardware architecture for consumer-grade zoned flash storage and comparing it with the state-of-the-art. We also make a case study for read performance research with ConZone to explore the design of mapping mechanisms and cache management strategies.

3D NAND high-density flash memory is widely used in edge computing, IoT, and automotive applications due to its high performance, low latency, and low storage cost characteristics. These scenarios require operation in extreme temperature environments, with cross-temperature read/write occurring frequently. However, cross-temperature affects programming reliability, leading to high raw bit error rates (RBER), which degrades read performance and increases energy consumption. In this paper, we propose a novel temperature-aware differential programming (TADP) scheme to optimize read performance and energy consumption under cross-temperature read/write. Specifically, first, a temperature-aware compensatory programming scheme is proposed to reduce the cross-temperature-induced degradation of RBER. Second, a layer variation-aware compensatory programming scheme is proposed to reduce the compensatory programming latency. Finally, a degraded programming scheme is proposed to enhance the temperature toughness of poorly temperature-tough word-lines by using them as MLC. Evaluated on 233-layer 3D triple-level-cell (TLC) NAND flash, TADP achieved encouraging optimizations in programming reliability, energy consumption, and read performance with minimal capacity loss.

Modern mobile devices adopt two-level memory swapping consisting of ZRAM and storage devices to relieve memory pressure. In the swap subsystem, ZRAM can improve application responsiveness and reduce write traffic to storage devices while consuming physical memory and additional CPU cycles. To better utilize ZRAM and improve system performance, we propose ElasticZRAM, an elastic ZRAM to redesign the traditional memory swapping with full awareness of the characteristics of applications and NAND flash-based storage devices on mobile devices. Experimental results on Google Pixel 6 demonstrate that ElasticZRAM improves application response time by up to 24.8% with negligible overhead compared with state-of-the-arts.

The pseudo-single-level-cell (pSLC) technique is widely adopted in high-density flash-based storage to mitigate the performance and endurance problem of high-density flash memory. Furthermore, prefetching schemes can compensate for performance differences among storage tiers. Existing prefetchers are implemented in the operating system (OS) or storage layers. However, OS layer prefetchers are conservative since it is a challenge to achieve both high accuracy and large coverage simultaneously. Storage layer prefetchers are sub-optimal due to the performance differences between pSLC and DRAM. In this paper, a cross-layer prefetching framework (CPF) is proposed to prefetch data selectively. The basic idea is that high-accuracy data will be prefetched to DRAM and large-coverage data will be prefetched to the pSLC flash in storage. To make it practical, an adaptive regulator is further designed to dynamically adjust the cross-layer prefetching to ensure accuracy and coverage. Evaluations show that CPF can improve read performance and reduce data transfer costs significantly.

Mobile devices always cache numerous files during application runtime, which can be trimmed to improve the user experience. However, existing cache file trimming methods are unaware of the cleaning cost within the file system and storage devices, which degrades the system performance and storage lifetime, resulting in low benefits of trimming cache files. Motivated by this, an adaptive cache file trimming (CacheTrimmer) scheme is proposed to trim cache files for performance and lifetime improvement. The basic idea is to determine the trimming timing based on the cleaning cost of the file system and storage device, maximizing the benefit of trimming cache files. Specifically, CacheTrimmer includes two components: First, a cleaning cost-aware trimming method is proposed to trim cache files by recording the index information of cache files in a list and determining the timing and size of file trimming. Second, to avoid trimming-induced intra-segment fragmentation and improve trimming efficiency, a log-structured cache scheme is further proposed to maintain the cache files in separate segments. We prototype CacheTrimmer with a real mobile platform. Experimental results under real workloads show that CacheTrimmer achieves encourage performance and lifetime improvement compared to the state-of-the-art.

WriteBooster is widely adopted as a non-volatile write buffer to enhance user experience for smartphones. How-ever, the host suffers sub-optimal write performance when using WriteBooster due to the lack of utilization of rich semantic infor-mation. With the zoned storage being included in smartphones, WriteBooster design presents new opportunities. In this paper, we propose Zoned-WB, a WriteBooster management scheme based on zoned storage to utilize the rich semantic information on the host to improve user experience. Specifically, Zoned- Wbincludes two parts, zoned storage-based WB and foreground request-aware WB. First, the zoned storage-based WB is aimed at designing WriteBooster management scheme based on zoned storage. Second, foreground request-aware WB is designed to adaptively adjust the capacity quota for different types of requests in Writebooster based on rich semantic information on the host. We evaluate Zoned-WB on a zoned storage emulator with workloads collected from smartphones. Evaluation results show that Zoned- Wbcan effectively improve user experience.

Hybrid flash-based storage constructed with high-density and low-cost flash memory has become increasingly popular in consumer devices in the last decade due to its low cost. However, its poor reliability is one of the major concerns. To protect critical data for guaranteeing user experience, some methods are proposed to improve the reliability of consumer devices with non-hybrid flash storage. However, with the widespread use of hybrid storage, these methods will result in severe problems, including significant performance and endurance degradation. This is caused by the fact that the different characteristics of flash memory in hybrid storage are not considered, e.g., performance, endurance, and access granularity. To address these problems, a critical data backup (CDB) design is proposed to ensure critical data reliability at a low cost. The basic idea is to accumulate two copies of critical data in the fast memory first to make full use of its performance and endurance. Then, one copy will be migrated to the slow memory in the stripe to avoid the write amplification caused by different access granularity between them. By respecting the different characteristics of flash memory in hybrid storage, CDB can achieve encouraging performance and endurance improvement compared with the state-of-the-art. Furthermore, to avoid performance and lifetime degradation caused by the backup data occupying too much space of fast memory, CDB Pro is designed. Two advanced schemes are integrated. One is making use of the pseudo-single-level-cell (pSLC) technique to make a part of slow memory become high-performance. By supplying some high-performance space, data will be fully updated before being evicted to slow memory. More invalid data are generated which reduces eviction costs. Another is to categorize data into three types according to their different life cycles. By putting the same type of data in a block, the eviction efficiency is improved. Therefore, both can improve device performance and lifetime based on CDB. Experiments are conducted to prove the efficiency of CDB and CDB Pro. Experimental results show that compared with the state-of-the-arts, CDB can ensure critical data reliability with lower device performance and lifetime loss whereas CDB Pro can diminish the loss further.

Hybrid solid state drives (SSDs) that integrate high-performance and large-capacity flash are widely used due to their cost-effectiveness. The TRIM command, which is a popular command in normal SSDs to improve performance and endurance, is also recommended in hybrid SSDs. However, employing TRIM on hybrid SSDs as on normal SSDs will induce performance loss and sub-optimal endurance due to the different characteristics of flash in hybrid SSDs. To solve the problem, this paper first explores the critical factors of issuing TRIM commands to different flash. Then, this paper proposed a differential TRIM method (dTRIM), which suggests performing early TRIM on high-performance flash and lazy TRIM on high-capacity flash. Specifically, early TRIM will minimize garbage collection costs while lazy TRIM tries to avoid conflicting user requests. Experimental results demonstrate that dTRIM can significantly improve the performance and endurance of hybrid SSDs compared with the state-of-the-arts.

Hybrid flash based storage constructed with high-density and low-cost flash memory are becoming increasingly popular in consumer devices during the last decade. However, to protect critical data, existing methods are designed for improving reliability of consumer devices with non-hybrid flash storage. Based on evaluations and analysis, these methods will result in significant performance and lifetime degradation in consumer devices with hybrid storage. The reason is that different kinds of memory in hybrid storage have different characteristics, such as performance and access granularity. To address the above problems, a critical data backup (CDB) method is proposed to backup designated critical data with making full use of different kinds of memory in hybrid storage. Experiment results show that compared with the state-of-the-arts, CDB achieves encouraging performance and lifetime improvement.