Processing-in-memory (PIM) paradigm is a promising solution to minimize the cost of data movement in the von Neumann architecture. Many proposals have explored possibilities to realize this paradigm in the main memory leveraging DRAM technologies. DRAM-based PIM technology can be implemented in two ways: processing-in-memory with digital compute units in peripheral area and processing-using-memory (PUM). Although computing within memory cells without digital compute units at peripherals is certainly appealing, DRAM-based PUM architectures still have various limitations to overcome. In particular, we identify three major challenges to bring PUM closer to production: compatibility with commodity DRAM microarchitecture, reliability, and coverage of operations. To address these challenges, we propose PRADA, a Processing-using-Memory Architecture based on DRAM cell Array. Unlike existing proposals, PRADA does not introduce any changes to the highly optimized cell area by not utilizing either designated rows for computation or dual-contact cells (DCCs) to implement NOT operation. Instead, PRADA proposes two new states in the bitline sense amplifier (BLSA) to implement NOT operation without any new additional circuitry. We also demonstrate how to implement various operations in PRADA, not only bit-wise logical operations but also both integer (INT) and floating-point (FP) arithmetic operations, while ensuring reliable bitline (BL) sensing. Compared to state-of-the-art PUM architectures, PRADA demonstrates 2.67--4.79× higher throughput for 8-bit integer multiply. For vector-ADD, PRADA achieves 3.09--3.13× speedups over the baseline, outperforming the other PUM architectures which show 1.04--2.07× speedups, while maintaining superior compatibility and reliability.

For efficient DNN inference Resistive RAM (ReRAM) crossbars have emerged as a promising building block to compute matrix multiplication in an area- and power-efficient manner. To improve inference throughput sparse models can be deployed on the ReRAM-based DNN accelerator. While unstructured pruning maintains both high accuracy and high sparsity, it performs poorly on the crossbar architecture due to the irregular locations of pruned weights. Meanwhile, due to the non-ideality of ReRAM cells and the high cost of ADCs, matrix multiplication is usually performed at a fine granularity, called Operation Unit (OU), along both wordline and bitline dimensions. While fine-grained, OU- based row compression (ORC) has recently been proposed to increase weight compression ratio, significant performance potentials are still left on the table due to sub-optimal weight mappings. Thus, we propose a novel weight mapping scheme that effectively clusters zero weights via OU-level filter reordering, hence improving the effective weight compression ratio. We also introduce a weight recovery scheme to further improve accuracy or compression ratio, or both. Our evaluation with three popular DNNs demonstrates that the proposed scheme effectively eliminates redundant weights in the crossbar array and hence ineffectual computation to achieve 3.27--4.26× of array compression ratio with negligible accuracy loss over the baseline ReRAM-based DNN accelerator.