EDBT 2026 Demo / reviewers in the wild / expert
Samaneh Naderi
dblp:327/1966
· DBLP profile ↗
1ranked-venue papers
0as first author
1since 2021 · last 2022
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1 · 1 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Hardware accelerators and domain-specific architectures · 77% Processor architecture and microarchitecture · 23% |
Topics — the 2 heaviest of 3, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Hardware accelerators and domain-specific architectures › domain-specific accelerator
sorting accelerator |
0.6 | 1 | 2022 | A fast and low-cost comparison-free sorting engine with unary computing: late breaking results · DAC 2022 |
Processor architecture and microarchitecture › computer arithmetic
unary computing |
0.2 | 1 | 2022 | A fast and low-cost comparison-free sorting engine with unary computing: late breaking results · DAC 2022 |
Methods — techniques the papers use, named apart from their topics
iterative maximum finding · 0.6comparison-free sorting · 0.6
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2022 | A fast and low-cost comparison-free sorting engine with unary computing: late breaking resultsabstractHardware-efficient implementation of sorting operation is crucial for numerous applications, particularly when fast and energy-efficient sorting of data is desired. Unary computing has been used for low-cost hardware sorting. This work proposes a comparison-free unary sorting engine by iteratively finding maximum values. Synthesis results show up to 81% reduction in hardware area compared to the state-of-the-art unary sorting design. By processing right-aligned unary bit-streams, our unary sorter is able to sort many inputs in fewer clock cycles. Amir Hossein Jalilvand, Seyedeh Newsha Estiri, Samaneh Naderi, M. Hassan Najafi, Mohsen Imani |
DAC | 3 |