This paper presents the process of generating the layout of the 8-bit Successive Approximation Register Analog to Digital Converter (SAR ADC). By utilizing LAYGO2 [1], a Python framework that allows for detailed and flexible specification of custom layout generation processes, code-based generators for the component blocks of a SAR ADC were developed according to their specific operational characteristics and requirements. As a result, 85.5% of the SAR ADC was automatically generated. The SAR ADC test chip was fabricated in a 14-nm CMOS FinFET process and achieved an SNDR of 41.67 dB at 500 MS/s, consuming 2.07 mW from 0.9 V supply, and occupying an area of 4,131 um2.

This paper presents a 56-Gb/s 3-tap feed-forward equalizer (FFE) four-level pulse-amplitude modulation (PAM-4) transmitter (TX) frontend for wireline applications. The proposed transmitter frontend operates at a 0.85-V termination voltage utilizing external surface-mounted (SMT) bias-tees. Unlike conventional tail-less current-mode logic (CML) drivers with variable gate biases, the transmitter frontend employs shunt-FFE for fewer variations in output common-mode levels. The design is fabricated in 40-nm CMOS technology and occupies 0.021 mm2. The proposed PAM-4 transmitter design operating at 56 Gb/s consumes 22.0 mW from 0.85-V supply voltage, achieving 0.39-pJ/bit energy efficiency.

A 96-Gb/s PAM-8 transmitter with a transition-boosted current-mode logic (TBCML) driver is introduced and fabricated in 40-nm CMOS technology. The proposed TBCML driver incorporates cross-coupled gate voltage boosting and feedforward coupling techniques to enhance transition speeds for high-speed operation. The implemented transmitter achieves a differential peak-to-peak output swing of 657 mV at a data rate of 96 Gb/s. Feedforward equalization (FFE) is applied to mitigate inter-symbol interference (ISI). The prototype transmitter occupies a die area of 0.15 mm2and achieves an energy efficiency of 4.33 pJ/b with a total power consumption of 416 mW.