The increasing use of electric vehicles (EVs) has highlighted the need for sustainable recycling and traceability of essential raw materials. This study introduces a blockchain and AI-integrated framework designed with the possibility to optimize vehicle components lifecycle management with recycling and tracing throughout the supply chain. The system uses Decentralized Identifiers (DIDs) for secure identification of components, enabling transparent tracking from production to recycling. Hyperledger Fabric ensures immutable data an choring across stakeholders. Hyperledger Caliper is used for benchmarking the system, assessing metrics such as transaction speed, latency, and scalability. AI models, including regression and clustering algorithms, are utilized to optimize recycling processes, predict component lifespans, and enhance resource recovery in the system. A tokenized reward mechanism incentivizes eco-friendly practices among stakeholders. The system also shows its environmental benefits, including energy savings from improved recycling performance. The proposed framework effectively supports the circular economy by enhancing resource recovery processes. While its design has the potential to reduce environmental impact, this benefit depends on the reusable, modular system design.

The rapid evolution of digital identity verification demands solutions that balance security, privacy, and efficiency. The electronic know your customer (eKYC) is a technological integration for client identification. It automates the process, reducing costs related to traditional know your customer (KYC). This includes eliminating paper-based document management, reducing manpower needs, and minimizing human errors. This systematic literature review (SLR) uses the preferred reporting items for systematic reviews and meta-analyses (PRISMA) model to investigate the revolutionary potential of blockchain-based electronic KYC (eKYC), focusing on self-sovereign identity (SSI) and Decentralized Identifiers (DID). The evaluation summarizes the current state by critically assessing 44 selected research works from an initial pool of 367. Our findings show that decentralized eKYC improves security with tamper-proof credentials and cryptographic verification. SSI and DID give users control over their data and selective disclosure. However, there are key limitations: 1) a focus on financial applications, ignoring Internet of Things (IoT) integration; 2) a lack of comprehensive technical analysis on scalability and interoperability; and 3) limited real-world case studies on regulatory compliance and challenges. This work combines insights from research and industry, highlighting the need for regulatory collaboration, hybrid architectures for scalability, and user-centric design. In addition, most identity management solutions are based on Ethereum (33%), followed by Hyperledger (18%). Around 51% of solutions use smart contracts, with banking (23%) and the financial industries (19%) being the primary adopters. It emphasizes the importance of standardized eKYC protocols, technical evaluations, and interdisciplinary collaboration for practical adoption across sectors.

Nowadays, cryptographic computation across various security applications necessitates the development of hardware that is not only fast and power-efficient but also flexible enough to support a range of cryptographic algorithms. Unfortunately, existing computing platforms for cryptography struggle to balance high flexibility, high performance, and low power consumption. To address these issues, this article introduces the crypto-tailored flexible engine (CTFE), a next-generation coarse-grained reconfigurable array (CGRA) for cryptography. Concretely, the CTFE incorporates four innovative ideas to achieve high flexibility and performance with high hardware efficiency: 1) processing element array (PEA) with dual-buffer lanes and multiplexer optimization; 2) high flexibility Hyper-ALU; 3) heterogeneous PEA; and 4) bi-tiered pipeline coordination. Real-time evaluation results on Xilinx ZCU102 FPGA at the System-on-Chip (SoC) level demonstrate that the CTFE is 1.13–14.3 times better in throughput and 55.3–14 232 times better in energy efficiency than state-of-the-art CPUs. Experiments on an ASIC 45 nm CMOS technology show that the CTFE consumes the power of 1.06 W, occupies an area of$2.77 \; \text {mm}^{{2}}$, and operates at the frequency of 510 MHz. In comparison to existing CGRA solutions, CTFE outperforms 1.63–20.23 times in throughput and 1.61–73.2 times in area efficiency.

Blockchain distributed ledger technology (DLT) has widespread applications in society 5.0 because it improves service efficiency and significantly reduces labor costs. However, employing blockchain DLT entails considerable energy consumption in the mining process. This paper proposes a blockchain accelerator (BCA) with ultralow power consumption and a high processing rate to address the problem. The BCA focuses on accelerating the double secure hash algorithm (SHA) 256 function required in the mining process at a system-on-chip (SoC) level. We propose three ideas, namely, multiple local memories (multimem), double-cell processing element (D-PE), and nonce autoupdate (NAU), to reduce the external data transfer time and improve the BCA hardware efficiency. We propose a cascaded multiple BCA chip model to enhance the system throughput by several-fold. Our experiments on an ASIC and FPGA prove that the proposed BCA successfully performs the mining process for multiple blockchain networks with much lower power consumption than that of the state-of-the-art CPUs and GPUs. The BCA is laid out with Renesas 65 nm technology with a chip area of$25~mm^{2}$and consumes$530~mW$at 100MHz. The power efficiency of the layout chip is improved by 2428 and 143 times compared with that of the fastest CPU Intel i9-10940X and GPU RTX 3090, respectively.

In visible light communication (VLC) system, flicker mitigation is considered as an essential requirement that can be met by the use of run-length limited (RLL) code. Among researches about RLL code, soft input soft output (SISO) RLL decoding scheme is proved significantly improving the error correction performance of the entire VLC system. However, it suffers from high computational complexity. To overcome this limitation, this paper proposed a deep learning framework that effectively performs the RLL decoding at a VLC receiver. The proposed framework makes use of a one-layer long short term memory (LSTM) followed by a fully-connected layer to learn the input-output relation of RLL decoder. Additionally, we present numerical results to validate the excellent performance of the proposed RLL decoder. The results exhibit that the combination between FEC and DL-based RLL approach is capable of achieving the bit error rate (BER) performance of concatenated FEC and SISO RLL decoder; while substantially reducing computational complexity.

This paper proposes a hardware architecture of K-best-based 4 × 4 MIMO decoder that supports up to 256-QAM. The novelties such as Direct Expansion, and 2D Sorter play important roles on reducing the complexity of the decoder. In addition, the most complex operators such as divider and multiplier are eliminated in this design. As compared to the previous works, the proposed decoder achieves the highest throughput (up to 2.7 Gbps), consumes the least power (56 mW), and obtains the best hardware efficiency(15.2 Mbps/Kgate).

Although the K-best algorithm is well-known as an efficient suboptimal version of the maximum likelihood detection (MLD), its complexity is still significantly affected by the constellation size W. Especially, its sorting task is known as the major bottleneck. In this paper we propose a two dimensional (2D) sorter-based K-best algorithm, whose complexity is negligibly affected by W. Instead of considering all of the constellation nodes as the full K-best does, our algorithm specifies the best nodes directly and processes these nodes only. In addition, the notion of 2D sorter is introduced to simplify the sorting task. The paper shows that the complexity of our algorithm is 87 times less than that of the full K-best. It is also less complex than the conventional works. In terms of BER performance, our algorithm outperforms the BLAST MMSE, LRA-MMSE, and is close to the full K-best.

In this paper, we present an efficient and high throughput hardware implementation of the RC4 algorithm. The main idea of the proposed architecture is the utilization of a tri-port RAM to reduce the memory resource and to increase throughput. The proposed design requires two clock cycles for generating one byte of ciphering key and uses only a block of 256 bytes RAM. These result in 50% increment of system throughput and three times reduction of RAM resource compared to the recent architectures. The proposed implementation supports variable key length from 8 to 128 bits and achieves 80 MB/s throughput at 160 MHz operating frequency. It aims to support the WEP security in the MAC layer of 600 Mbps 4×4 MIMO wireless LAN system based on IEEE 802.11n standard.