In-Memory Computing (IMC) has emerged as one of the most promising architectures to efficiently compute artificial intelligence tasks on hardware, particularly Deep Neural Networks (DNNs). IMC can make use of analog computation principles alongside emerging Non-Volatile Memory (eNVM) technologies, potentially offering several orders of magnitude increased energy efficiency compared to generic processing units. Yet, the use of analog circuitry, potentially integrated with emerging technologies post-processed on top of silicon wafers, increases the susceptibility of hardware to a large spectrum of variations, for instance manufacturing, noise or temperature sensitivity. Hence, this susceptibility can hamper the large-scale deployment of IMC circuits into the market. To tackle the reliability of analog resistive-based IMC circuits regarding temperature variations, this paper presents TRIM, a thermal on-chip auto-compensation method aimed at fully calibrating first-order temperature effects. TRIM is designed to maintain the computational accuracy of IMC cores in DNN applications over a wide temperature range, while being highly scalable and adaptable. In essence, the temperature compensation is realized through a Complementary-To-Absolute-Temperature (CTAT) voltage reference integrated inside a voltage regulator and applied at the zero reference node of a Multiplying Digital-to-Analog Converter (MDAC), eliminating the need for external circuits or look-up tables. The proposed methodology is demonstrated on a proof-of-concept 65 nm CMOS resistive IMC column. Measurement results showcase that the proof-of-concept auto-compensation system significantly enhances inference and Multiply-And-Accumulate (MAC) operation accuracy of any first-order resistive crossbar column, achieving inference accuracy recovery of 100% over a temperature range of -20 ∘C to 60 ∘C and a 91.3 in MAC operation accuracy, with an area overhead of 2% and power overhead of <0.02%.

This work presents a sub-100 nW all-in-one voltage and current reference circuit implemented using 600 nm indium gallium zinc oxide (IGZO) thin-film transistor (TFT) on a flexible substrate. The proposed design integrates both voltage and current references into a single, simple, and compact architecture. By employing NMOS-only devices with negative feedback, the circuit achieves temperature compensation over a temperature range from 10 °C to 100 °C through a stabilized zero temperature coefficient (ZTC) bias point, enhancing the temperature coefficients (TCs). Simulation results demonstrate that the circuit provides a stable reference current of 78.14 nA and a reference voltage of 1.153 V at room temperature (27 °C), with TCs of 99.6 ppm/°C and 263.6 ppm/°C, respectively. The line sensitivities (LS) are 1.276%/V for the current reference and 0.319%/V for the voltage reference over a supply voltage range from 1.5 V to 5 V making it suitable for integration into both flexible electronics and even conventional Si-based CMOS circuits. The circuit achieves a current efficiency of 99.95% and occupies an area of 0.0183 mm2.

As the global population ages, caregivers encounter significant challenges in monitoring wet diapers and assessing the volumes of voided fluids in adult incontinence products. Recent advancements in smart-diaper technology address these issues, but challenges persist with integrating electronics, frequent removal and reapplication, and managing batteries. This study presents a batteryless urine-powered IoT sensor node using printed energy harvesters and capacitive sensors integrated with an ultra-low-power integrated circuit for disposable smart diapers. Coplanar capacitive sensors and electrochemical energy harvesters are printed on the flexible substrate using environment-friendly materials. An ultra-low power frontend interface is developed, which is powered by the harvested energy from urine. Laboratory measurements validate the functionality of on-chip electronics and the performance of in-diaper sensors and energy harvesters. The system demonstrates effective energy harvesting by maintaining a stable regulated voltage of 1.1 V with urine volumes of 90 ml or more, powering the front-end electronics continuously for 6 hours. The proposed system successfully demonstrated the detection of multiple urination events in the diaper and quantified the voided volume as low as 30 ml. The results demonstrated in this work pave the way for cost-effective, disposable, and environmentally friendly solutions for smart diapers, enhancing both efficiency and comfort for caregivers and elderly individuals.

In-memory computing (IMC) accelerators have become a pivotal architecture for enhancing AI algorithm computations, particularly critical for embedding deep neural networks (DNNs) in edge devices. The efficiency of these systems is paramount, yet IMC cores are prone to fluctuations due to process, temperature, and voltage variations, which can detrimentally impact DNN accuracy. This research introduces an innovative Built-In Self-Calibration (BISC) methodology, specifically designed to compensate for temperature-induced variations in mixed-signal IMC cores. The methodology enables real-time, on-chip adjustment of DNN weights during computation within the IMC core without modifying the computation path. The proposed approach, implemented on a silicon prototype, not only maintained DNN computation accuracy under substantial temperature variations but also fully compensated for almost 90% of the offset caused by these variations, without introducing any non-idealities.

This work presents a versatile all-NMOS circuit with dual functions, i.e. either as a conventional temperature sensor or as a precise voltage reference, meeting the vital demand for multi-functional, reusable circuits, thus reducing chip area and power consumption constraints. The circuit can measure temperature in one mode and guarantee the reliable function of implants/wearables by delivering a temperature invariant stable reference voltage in the other mode. The circuit works for a wide temperature range of -40°C to 80°C, without needing extra circuits such as operational amplifiers, startup circuits, or resistors. Implemented in a 65 nm bulk CMOS technology, the circuit occupies an area of 0.00393 mm2. The mode of operation can be controlled by a mode control bit. In voltage reference mode, the circuit has a low temperature coefficient of 96 ppm/°C with an output voltage of 604.3 mV at room temperature. The line sensitivity of the circuit is 0.397 %/V in the operation range of 0.7 V to 1.2 V, consuming a power of 21.23 nW. In the temperature sensing mode, the circuit consumes a power of 42.75 nW, with a temperature inaccuracy of +0.929°C/-1.42°C.

In-Memory Computing (IMC) architectures promise increased energy-efficiency for embedded artificial intelligence. Many IMC circuits rely on analog computation, which is more sensitive to process and temperature variations than digital. Thus, maintaining a suitable computation accuracy may require process and temperature compensation. Focusing on resistive-based IMC architectures, we propose an ultra-low power circuit to compensate for the temperature and process-based non-linearities of resistive computing elements. The proposed circuit, implemented in 65 nm CMOS can provide a temperature coefficient between 10 and 1938 ppm/°C for a wide temperature range (-40°C to 80°C) and output current range (few pA up to 600 nA) at 1.2 V operating voltage. Used in a resistive IMC array, the variation of output currents from each multiply-accumulate (MAC) operation can be reduced by up to 84% to maintain computation accuracy across process and temperature variations.