Demo Data from EDBT 2026 / reviewers in the wild / expert
Tim-Marek Thomas
dblp:327/6926
· DBLP profile ↗
3ranked-venue papers
1as first author
3since 2021 · last 2024
0009-0000-8197-2423ORCID · corroborated
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 2 · 2 since 2021Security and privacy · 1 · 1 first-author · 1 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Network and information security
1 paper |
Systems and software security · 100% | |
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Processor architecture and microarchitecture · 100% | |
| Software engineering, system software, and programming languages
1 paper |
Operating systems · 100% |
Topics — the 4 heaviest of 5, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Systems and software security
memory safety |
0.8 | 1 | 2024 | KPAC: Efficient Emulation of the ARM Pointer Authentication Instructions · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2024 |
Systems and software security › memory protection
pointer authentication |
0.8 | 1 | 2024 | KPAC: Efficient Emulation of the ARM Pointer Authentication Instructions · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2024 |
Systems and software security › memory safety
return address protection |
0.8 | 1 | 2024 | KPAC: Efficient Emulation of the ARM Pointer Authentication Instructions · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2024 |
Processor architecture and microarchitecture
instruction set architecture |
0.8 | 1 | 2024 | KPAC: Efficient Emulation of the ARM Pointer Authentication Instructions · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2024 |
Methods — techniques the papers use, named apart from their topics
trap-based emulation · 2.3memory-based invocation · 2.3
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2024 | KPAC: Efficient Emulation of the ARM Pointer Authentication InstructionsabstractARMv8.3-A has introduced the pointer authentication (PA) feature, a new set of measures and instructions to sign and validate pointers. PA is already used and supported by the major compilers to protect the return addresses on the stack as a measure against memory corruption attacks. As more and more SoCs implement ARMv8.3-A and code compiled with PA is even fully backwards compatible on CPUs without (where the new instructions are just ignored), we can expect PA-enabled binaries to become standard in the near future. This gives rise to the question, if and how also systems without the native PA could benefit from the extra security provided by the return address protection. In this article, we explore KPAC, a set of efficient software-based approaches to bring the PA-based return-address protection onto the platforms without the hardware support in an easily adoptable (binary-compatible) and scalable manner. Technically, KPAC achieves this by either a synchronous trap-based emulation inside the kernel or an asynchronous novel memory-based invocation of a dedicated CPU core. Our experiments with the CortexSuite benchmarks, Chromium, and Memcached on a variety of platforms running Linux ranging from a Xilinx ZCU102 board over a Raspberry Pi 4 up to an 80-core Ampere Altra demonstrate the broad applicability and scalability of our approach. Furthermore, we discuss how the principles of KPAC can be generalized to the other suited problem areas. Illia Ostapyshyn, Gabriele Serra, Tim-Marek Thomas, Daniel Lohmann |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 3 |
| 2023 | Checkpoint Placement for Systematic Fault-Injection CampaignsabstractShrinking hardware structures and decreasing operating voltages lead to an increasing number of transient hardware faults, which thus become a core problem to consider for safety-critical systems. Here, systematic fault injection (FI), where one program-under-test is systematically stressed with faults, provides an in-depth resilience analysis in the presence of faults. However, FI campaigns require many independent injection experiments and, combined, long run times, especially if we aim for a high coverage of the fault space. One cost factor is the forwarding phase, which is the time required to bring the system-under test into the fault-free state at injection time. One common technique to speed up the forwarding are checkpoints of the fault-free system state at fixed points in time. In this paper, we show that the placement of checkpoints has a significant influence on the required forwarding cycles, especially if we place faults non-uniformly on the time axis. For this, we discuss the checkpoint-selection problem in general, formalize it as a maximum-weight reward path problem in graphs, propose an ILP formulation and a dynamic programming algorithm that find the optimal solution, and provide a heuristic checkpoint-selection method based on a genetic algorithm. Applied to the MiBench benchmark suite, our approach consistently reduces the forward-phase cycles by at least 88 percent and up to 99.934 percent when placing 16 checkpoints. Christian Dietrich 0001, Tim-Marek Thomas, Matthias Mnich |
ICCAD | 2 |
| 2022 | ACTOR: Accelerating Fault Injection Campaigns Using Timeout Detection Based on Autocorrelation
Tim-Marek Thomas, Christian Dietrich 0001, Oskar Pusz, Daniel Lohmann |
SAFECOMP | 1 |