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Qiyue Huang

dblp:327/7182 · DBLP profile ↗
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2ranked-venue papers
0as first author
2since 2021 · last 2025
0000-0003-0375-1136ORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2 · 2 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Hardware accelerators and domain-specific architectures · 100%
Artificial intelligence
1 paper
Efficient and distributed learning · 100%

Topics — the 5 heaviest of 5, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Machine learning › Efficient and distributed learning
model compression
0.912025
Vision Transformer Acceleration via a Versatile Attention Optimization Framework · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2025
Machine learning › Efficient and distributed learning › model compression
quantization and sparsification
0.912025
Vision Transformer Acceleration via a Versatile Attention Optimization Framework · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2025
Hardware accelerators and domain-specific architectures › machine learning accelerator
attention mechanism optimization
0.912025
Vision Transformer Acceleration via a Versatile Attention Optimization Framework · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2025
Hardware accelerators and domain-specific architectures
machine learning accelerator
0.912025
Vision Transformer Acceleration via a Versatile Attention Optimization Framework · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2025
Hardware accelerators and domain-specific architectures › machine learning accelerator › transformer accelerator
vision transformer accelerator
0.912025
Vision Transformer Acceleration via a Versatile Attention Optimization Framework · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2025

Methods — techniques the papers use, named apart from their topics

systolic array · 1.7spquant algorithm · 1.7sparse-sparse matrix multiplication · 1.7
YearPublicationVenuePosition
2025 Vision Transformer Acceleration via a Versatile Attention Optimization Framework
abstract
Vision Transformers (ViTs) have achieved remarkable success across various tasks. However, their deployment is hindered by challenges, such as high memory requirements, long inference latency, and significant power consumption. To address these challenges, existing works optimize one of the two key stages on ViT’s critical path: linear projection or self-attention. Regrettably, we have noticed that both linear projection and self-attention can potentially become bottlenecks as the input image resolution varies, which makes the existing approaches lack generality. Accordingly, in this article, we propose a versatile attention optimization framework. On the algorithm side, we present a SpQuant algorithm that sparsifies weight matrices offline and input matrices online during linear projection as well as tunes the bit-width of the probabilities matrix according to their importance. On the hardware side, we design SQArch architectures to improve the performance of the SpQuant algorithm. The proposed SQArch architecture offers a low-cost preprocess module that predicts and prunes nonkey elements of the input matrix on the fly. Moreover, we design a compute module that supports sparse-sparse matrix multiplications (SpMSpM) and multiple precision computations on a single systolic array for generality. Furthermore, we can address the underutilization and workload imbalance problems by 1) decoupling the rows in the systolic array for enough flexibility and 2) proposing a workload balance scheme for SpMSpM that allows the array to accept data of similar sparsity, thereby reducing synchronization between computing units. Extensive experiment results demonstrate that SQArch can achieve satisfactory performance speedups and energy saving compared to state-of-the-art designs.
Xuhang Wang, Qiyue Huang, Xing Li 0031, Haozhe Jiang, Qiang Xu 0001, Xiaoyao Liang, Zhuoran Song
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.2
2023 DEQ: Dynamic Element-wise Quantization for Efficient Attention Architecture
abstract
Attention-based models, such as transformers, have achieved remarkable success across various tasks. However, their deployment is hindered by challenges such as high memory requirements, long inference latency, and significant power consumption. Quantization has emerged as an effective approach to address these challenges by reducing the bit-width of the model. However, existing quantization algorithms suffer from too coarse-grained quantization granularity or statically determining the bit-width of tokens, lacking the flexibility needed to achieve maximum performance improvement. Accordingly, in this paper, we present a Dynamic Element-wise Quantization (DEQ) algorithm that dynamically tunes tokens’ bit-width according to the importance of elements in the attention possibilities matrix.On the hardware side, we design three versions of DEQ architectures to progressively improve the performance of the DEQ algorithm. The proposed DEQ architecture can address the under-utilization and workload imbalance problems by 1) supporting multiple precision computations on a single systolic array for generality, 2) decoupling the rows in the systolic array for enough flexibility, 3) identifying and parallelizing the independent computations within one systolic array for high parallelism. Extensive experiment results demonstrate that DEQ can achieve satisfactory performance speedups and energy saving compared to state-of-the-art designs.
Xuhang Wang, Zhuoran Song, Qiyue Huang, Xiaoyao Liang
ICCD3