Successful reverse engineering (RE) of digital signal processing (DSP) integrated circuits (ICs) by an attacker provides him/her a chance to pirate the DSP-based intellectual property (IP) and insert malicious logic. It is thus central to devise low-cost sturdy functional obfuscation techniques for DSP cores that hinders RE attempt (or increases attackers effort manifold). There has been meager effort on devising robust high-level synthesis (HLS) based functional obfuscation methodology that is low-cost/power. This paper presents a novel S ecure Hi gh- L evel synthesis based functional obfuscation methodology for E nhanced security of D SP cores called “ SHiELD ” that is driven through HLS based one-way random (OWR) function and reconfigurable composite switching obfuscation (CSO) cells, integrated with design space exploration process. The proposed approach offers security against different relevant attacks and in overall effectively thwarts RE attempt with the aid of proposed multi-key bit CSO cells, and custom OWR function. The results of the proposed approach in comparison with prior approaches yielded several magnitudes of higher security (robust obfuscation strength and lower probability of key retrieval) upto ∼10 154 (for FIR-2 benchmark calculated using Equation ( 1 )), lower power (of ∼10.6%) and reduction in design cost (of 0.91%).

Reusable third-party intellectual property (3PIP) cores within the supply chain are vulnerable to hardware threats such as IP piracy and false claim of ownership. Securing the reusable IP cores is vital to protect the original vendor from a substantial revenue loss and his/her brand value. This paper presents a novel hardware IP core watermarking methodology based on voice biometric signature to enable detective control against IP piracy and resolve IP ownership claim. To the best of our knowledge, this is the first voice biometric-based hardware IP protection technique. This paper proposes a novel methodology for generating a unique voice signature template using distinct voice features, viz. jitter and shimmer, along with pitch and intensity values at different timestamps. We present a high-level synthesis (HLS) design methodology of embedding a voice signature digital template during the register allocation phase to generate secured IP cores. Results and analysis imply that the proposed approach can significantly improve security in terms of stronger authorship proof and higher tamper tolerance compared to the existing IP watermarking approaches. Additionally, we also analyze the uniqueness of a voice signature and its security against forgery attack. We achieve higher security at negligible design cost overhead.

This paper presents a novel hardware security technique that leverages handwritten signature image features for securing intellectual property (IP) cores, such as digital signal processing (DSP) cores, against IP piracy and false claim of IP ownership threats. In our approach, an IP vendor's handwritten signature image features are first converted into a corresponding digital template, followed by mapping into hardware security constraints and implanting them into the design during high level synthesis (HLS) process. This paper presents methodologies of extracting feature set of a handwritten signature through sampling and of encoding of the samples into binary values using a tree based encoding, for generating the digital template. The results of the proposed approach are assessed in terms of strength of IP ownership proof, security against a forged signature and impact of embedding signature constraints on design cost. The results revealed that the proposed approach provides robust security at negligible design cost overhead and also outperforms state of the art hardware security approaches for DSP cores.

This article proposes a robust encrypted protein molecular biometric signature-based hardware security approach to secure hardware accelerators (like digital signal processing (DSP) and multimedia intellectual property (IP) cores) against threats of piracy/IP counterfeiting and ownership abuse. In the proposed approach, protein molecular biometric signature is formulated by taking the protein sequence of 20 different unique amino acid combinations from human body protein sample, followed by robust encryption using facial biometric key and encodings. This IP vendor’s encrypted protein molecular biometric signature is then subsequently converted into its corresponding digital proof, followed by embedding into the design as a covert protein molecular signature security constraint, thus producing a secured hardware accelerator design. The proposed approach is more robust than recent hardware security approaches proposed in the literature in terms of stronger proof of ownership (authorship) as well as tamper tolerance (TT) ability. The results present the following analysis of the proposed protein molecular biometric signature approach: 1) very low probability of coincidence (Pc) metric (signifying strength of digital proof) for different DSP hardware accelerators in the range of 3.40E-13–6.33E-2 and 2) stronger TT ability in the range of 5.39E + 67–1.0E + 421 for different DSP hardware accelerators.