3D TLC NAND flash memory achieves high storage density due to multi-bit technology and vertical stacked structure, while suffering from severe reliability issues, particularly a high raw bit error rate (RBER). Accurate prediction of RBER in 3D TLC NAND flash memory enables proactive data management, thereby enhancing performance, improving reliability, and extending the lifetime of the memory. This paper focuses on accurately estimating the RBER of flash memory to provide more detailed information for the precise control and optimization strategies. In this paper, we propose a Hybrid Neural Network model (HNN) for RBER prediction, which combines the advantages of multi-layer perceptron (MLP) and recurrent neural network (RNN). The model utilizes a multi-layer perceptron (MLP) for static feature extraction and the gated recurrent unit (GRU) for time series analysis. By combining these approaches, the HNN can effectively capture the complex relationships and temporal patterns that affect the RBER. Experimental results, based on actual chip data, demonstrate that the HNN can predict the RBER with an r-squared value greater than 0.96, significantly outperforming traditional machine learning algorithms and neural networks.

Quad-level cell (QLC) has received significant attention recently due to its extremely high storage capacity. However, because of its poor reliability, QLC-based solid-state drives (SSDs) require a two-step programming to reduce the layer interference. But during the interval between two programming steps on the same wordline (WL), data could be invalidated from update operations, leading to invalid programming and degraded performance. To mitigate the performance loss, we propose the NV-APP scheme to minimize the program and verify pulses during the second-step programming. NV-APP integrates the no-verify (NV) scheme and the adaptive pulse programming scheme (APP). The NV scheme omits verify pulses of invalid verify voltages. The APP scheme adaptively increases the programming step voltage$(V_{\mathrm { step}})$to accelerate cells’ threshold voltage shift, reducing the number of both program and verify pulses. Device-level simulation results show that the NV-APP scheme reduces the total number of program pulses by an average of 27.03% and verify pulses by an average of 48.70% across various invalid cases during the second-step programming. Based on a modified 3-D QLC SSD simulator with typical traces, the experiments demonstrate that our scheme reduces two-step programming time by an average of 17% on partially invalid WLs, close to the 19.8% reduction achieved by the ideal scheme with no performance loss.