Non-linear functions are fundamental mathematical computations in the realms of digital signal processing and artificial intelligence applications. Despite efforts to develop hardware accelerators for non-linear functions, current methodologies exhibit shortcomings in achieving both high-speed and high-precision computations. This paper introduces a novel scheme for high-precision non-linear approximation that leverages piecewise polynomial computation. By employing quadratic approximation, we reduce the number of segments and introduce a fine-grained computation method to meticulously control computational resources. Our example design, synthesized using 40nm CMOS technology, occupies an area of 15123µm2and consumes a power of 3.48mW when operating at 1GHz. In comparison with the state-of-the-art research, the proposed design boasts a reduction of 76.6% in area and an 86.3% decrease in power consumption, while maintaining equivalent precision levels.

In this paper, we propose a high-radix generalized hyperbolic coordinate rotation digital computer (HGH-CORDIC). This algorithm not only computes logarithmic and exponential functions with any fixed base but also significantly reduces the number of iterations required compared to traditional CORDIC methods. Initially, we present the general iteration formulas for HGH-CORDIC. Subsequently, we discuss its pivotal convergence properties and selection criteria, exemplifying these with commonly used cases. Through extensive software simulations, we validate the theoretical foundations of our approach. Finally, we explore efficient hardware implementation strategies. Our analysis indicates that, relative to state-of-the-art radix-2 GH-CORDIC, the proposed HGH-CORDIC can decrease the number of iterations by more than$50\%$while maintaining comparable accuracy. Synthesized under the 28nm CMOS technology, the reports show that the reference circuit can save about$40\%$area and power consumption averagely for$2^{x}$and$log_{2}x$calculations compared with the latest CORDIC method.

Binary and decimal logarithms (BDLs) are commonly used in science and engineering. This brief presents a theory of the radix-4 generalized hyperbolic coordinate rotation digital computer (GH-CORDIC) to compute them directly. Compared with traditional hyperbolic CORDIC (TH-CORDIC), the two logarithms can be calculated without extra dividers or multipliers. Compared with the GH-CORDIC, this theory has low iterations under the same high precision. Through theoretical derivation and software simulation, we can find that the calculation accuracy can reach the magnitude of$10^{-7}$, and the number of iterations can be reduced by more than 50%. Through hardware implementation, the synthesis report shows that the proposed architecture can save 53.44% area and 46.36% power consumption compared with the latest radix-2 GH-CORDIC method.

In this paper, we propose a high-radix generalized hyperbolic coordinate rotation digital computer (HGH-CORDIC), which not only can compute the logarithmic and exponential functions with any fixed base, but also can reduce the number of iterations compared with the traditional CORDIC. First, we propose the general iteration formulas for HGH-CORDIC. Then we demonstrate its important convergence property and selection criteria, and illustrate them with the most commonly used examples. Through software simulation, we further prove the correctness of the theory. Finally, we analyze how to implement it efficiently in hardware. Compared with the state-of-the-art work, HGH-CORDIC can reduce the number of iterations by more than 50% with the same accuracy.

In this paper, we propose a feasible architecture with high precision and low resource consumption to compute the$N$th root of a floating-point number, which is mainly based on radix-4 SRT and 2-based Coordinate Rotation Digital Computer (CORDIC). Simulation results show that our method can achieve a relative error of the magnitude of 10−7. Under the same precision requirements, the hardware implementation results show a better performance of our design in terms of area, power, and absolute delay compared with the method based on the generalized hyperbolic CORDIC. After synthesizing it under the TSMC$40n$m CMOS technology, it can be obtained that our design can achieve an area consumption of$125465.80\ \mu m^{2}$and power consumption of 97.8062 mW at the highest frequency of 3.12 GHz.

Softmax is a common and complex activation function in Deep Neural Networks (DNN). However, it is a challenge to apply it efficiently in DNN training hardware accelerator. Therefore, we propose a high precision calculation method and architecture based on base-2 softmax, which has low hardware complexity than base-$e$softmax but can still be useful in DNN training. First, we simplify the hardware implementation complexity of calculating base-2 softmax. Second, we use the base-2 hyperbolic COordinate Rotation Digital Computer (CORDIC) to implement the core computation. Finally, we show that the proposed method can be used in DNN training through experiments. Moreover, with the same order of the magnitude of high precision, our hardware cost is lower than traditional base-$e$softmax or other alternative design methods. Under TSMC 28nm CMOS technology, an example design of our architecture has the area of$98787.43\mu m^{2}$and the power consumption of 24.72mW for circuit synthesis at the frequency of 1GHz.

The softmax function is widely used in deep neural networks (DNNs), its hardware performance plays an important role in the training and inference of DNN accelerators. However, due to the complexity of the traditional softmax, the existing hardware architectures are resource-consuming or have low precision. In order to address the challenges, we study a base-2 softmax function in terms of its suitability for neural network training and efficient hardware implementation. Compared to the classical base-$e$softmax function, the base-2 softmax function is a new softmax function that uses 2 as the exponential base instead of$e$. From the aspects of mathematical derivation and software simulation, we first demonstrate the feasibility and good accuracy of the base-2 softmax function in the application of neural network training. Then, we use the symmetric-mapping lookup table (SM-LUT) method to design a low-complexity architecture but with high precision to implement it. Under TSMC 28nm CMOS technology, an example design of our architecture has the area of$5676 ~\mu m^{2}$and the power consumption of 13.12 mW for circuit synthesis at the frequency of 3 GHz. Compared with the latest works, our architecture achieves the best performance and efficiency.