Demo Data from EDBT 2026 / reviewers in the wild / expert
John R. Carruthers
dblp:328/6437
· DBLP profile ↗
1ranked-venue papers
0as first author
0since 2021 · last 1987
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Applied, interdisciplinary, general and emerging computing · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Electronic design automation · 77% Integrated circuit design · 23% |
Topics — the 1 heaviest of 2, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Integrated circuit design
VLSI technology |
0.0 | 1 | 1987 | Analysis technology for VLSI fabrication · Proc. IEEE 1987 |
Methods — techniques the papers use, named apart from their topics
voltage contrast electron microscopy · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1987 | Analysis technology for VLSI fabricationabstractAs a result of the rapid development of Very Large Scale Integrated circuit (VLSI) technology, procedures for the analysis of these devices are evolving equally rapidly. While there are a number of factors involved with VLSI development, most are dependent on the exponentially increasing device complexity, as customers demand more and more low-cost reliable functions per chip. In order to accommodate this demand, technology is responding with a variety of changes. Individual feature size is decreasing and chip size and wafer size are increasing, concurrent with new material development and manufacturing process innovation. Smaller feature size implies thinner films, fewer atoms per active element, higher resolution, and tighter geometry control. Larger chips and wafers result in larger size samples and improved control over larger areas and volumes. New materials require new analytical procedures. Lower cost requires higher yields, and the demand for higher reliability means less tolerance to poor design margins and to the presence of defects. Altogether, in order to satisfy these concurrent but often conflicting demands, the prompt and accurate analysis of features, chips, materials, and wafers is required. Since large chips and wafers are expensive, analysis often must be performed nondestructively, on vanishingly small areas of larger and larger samples. Consequently, even recently developed analytical procedures may be of little value; they may not be sensitive, accurate, or fast enough to satisfy demands, or cannot tolerate large samples, or are damaging to the samples. In this paper the rapidly evolving field of analysis of VLSI devices is discussed, both from the point of view of physics of the analytical procedures, and the application of the analytical needs to device improvement. Most emphasis is placed on describing procedures applied to the analysis of structural or chemical properties of VLSI materials and devices, but some discussion is devoted to electrical property characterization by means of voltage contrast electron microscopy. While the individual procedures are discussed in moderate detail, the focus is on relating various techniques to each other, to provide a framework from which general analytical choices may be made. A fairly extensive bibliography of analytical procedures is provided. Eugene S. Meieran, Paul A. Flinn, John R. Carruthers |
Proc. IEEE | 3 |