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Eric Etheridge

dblp:328/6934 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 1987
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Applied, interdisciplinary, general and emerging computing · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Processor architecture and microarchitecture · 87% Performance modeling and evaluation · 13%

Topics — the 2 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Processor architecture and microarchitecture › special-purpose processor
digital signal processor		 0.011987
Digital signal processor for test and measurement environment · Proc. IEEE 1987
Processor architecture and microarchitecture › instruction-level parallelism
parallel instruction execution		 0.011987
Digital signal processor for test and measurement environment · Proc. IEEE 1987

Methods — techniques the papers use, named apart from their topics

parallel architecture · 0.0instruction fetch unit · 0.0address computation unit · 0.0
YearPublicationVenuePosition
1987 Digital signal processor for test and measurement environment
abstract
This paper describes a high-performance digital signal processor, TriStar, developed for signal processing applications in test and measuring instruments. It executes typical signal processing tasks with very high throughput because of the concurrent operation of three units: instruction fetch unit, arithmetic unit, and address computation unit. A parallel architecture in addition to single-cycle operations allows the TriStar to run signal processing algorithms with an efficiency never before available to an instrument designer.
Arif Kareem, Charles L. Saxe, Eric Etheridge, David McKinney
 Proc. IEEE3