Recently, digital ICs with high current slewing characteristics and tight supply voltage margin put increasing demand on the supply regulators. In this paper, an augmented DC-DC buck converter consisting of a lower-frequency main converter and a normally-off fast-switching secondary stage operating in parallel is proposed. The main-stage of the converter uses emulated-current-mode hysteretic control. For the auxiliary transient-suppression stage a nonlinear control scheme termed multiple-single-cycle nonlinear control (MSCNLC) is developed. The proposed augmented regulator improves the load transient response without compromising the overall efficiency of the converter, breaking the well-known efficiency vs. dynamic response trade-off. The high power-efficiency main-stage operating at$F_{sw}=500$kHz provides the steady-state DC regulation voltage. The auxiliary-stage adopts a small inductor of 100nH and is only activated when load transient events are detected, providing fast load response, minimizing output voltage deviation. The load transient events are detected through an output capacitor charge tracking circuit, which effectively makes the auxiliary-stage a fast Current-Controlled-Current-Source during transient response. The buck converter is designed for$V_{IN} =3$V-5.5V,$V_{OUT} =0.5$V-1.1V and$I_{LOAD} =0.5$A-8A. It is fabricated in$0.18~\mu $m BCD process. The measurement results show that with MSCNLC enabled, the undershoot and overshoot is reduced to 27mV and 58mV during the step-up and step-down response with 2.5A load step by a factor of close to 2, respectively. The recovery time is improved by ~1.7x.

There is a significant demand in systems-on-chip (SoCs) for a high-power efficiency low-dropout regulator (LDO) that provides lower dropout voltage, higher load current, and low quiescent current. A high-power supply rejection ratio (PSRR) at the mid-to-high frequency band (0.1–10 MHz) is crucial for LDO to generate low-noise power supplies when driven by switching power converters. However, this presents a significant challenge to enhancing the PSRR since the pass field-effect transistor (FET) operates in the deep triode region at high-current and dropout conditions. In this article, a parallel feed-forward current ripple rejection (PFFCRR) technique is proposed to improve the PSRR performance regardless of the operation region of the nMOS pass FET. The proposed approach senses the supply-induced current ripple and cancels the original ripple through a current path that runs parallel to the nMOS pass FET. The proposed LDO is fabricated in a 180-nm BCD process. The proposed LDO achieves a PSRR better than −35 dB up to 10 MHz at 300-mV dropout voltage with 0.5-A load current and a load capacitor of$2.2~\mu $F. The PFFCRR approach achieves a PSRR improvement of 18 dB at 1 MHz at 100-mV dropout voltage with a 2.15-A load current when the pass FET operates in the deep triode region. Moreover, the proposed LDO enhances the transient performance with an overshoot and an undershoot of 40.54 and 36.45 mV, respectively, against$\Delta {I}_{\text {LOAD}}$of 1 A with a slew rate of 1 A/$\mu $s.

The load transient response and unity gain bandwidth of DC-DC boost converters are primarily restricted by the presence of a right half plane zero (RHPZ). In this paper, a control scheme termed peak current fast feedback control (PFFC) is proposed to improve the load transient response without the need for additional power switches or passive components. In the proposed PFFC method, the closed loop output impedance ($Z_{OCL}$) is improved by reducing the DC value and by increasing the bandwidth of$Z_{OCL}$as compared to conventional peak current mode control (CPCM), thus improving the steady state and transient performance. The fast feedback (FFB) path is implemented within the error amplifier (EA) with an increase of only 2% in the active area as compared to CPCM. The boost converter is designed for$V_{OUT} =5\text{V}$,$V_{IN} =2.5\text{V}$-4.4V and$I_{LOAD} =10$mA-1A operating at a fixed frequency of 2MHz. Measurement results show that with PFFC enabled, the settling time reduces by$\sim 2.6\times $and the undershoot reduces by 62% to$12~\mu \text{s}$and 41mV respectively when compared to CPCM for 10mA to 1A load step at 2A/$\mu \text{s}$. The converter achieves a peak efficiency of 95.2% at 0.5W output power with$V_{IN} =4.4\text{V}$and load regulation of 9mV/A at$V_{IN} =2.5\text{V}$.

Robustness to electromagnetic interference (EMI) is one of the primary design aspects of state of the art automotive ICs like System Basis Chips (SBCs) which provide a wide range of analog, power regulation and digital functions on the same die. One of the primary sources of conducted EMI on the Local Interconnect Network (LIN) driver output is an integrated switching DC-DC regulator noise coupling through the parasitic substrate capacitance of the SBC. In this paper an adaptive active EMI cancellation technique to cancel the switching noise of the DC-DC regulator on the LIN driver output to ensure electromagnetic compatibility (EMC) is presented. The proposed active EMI cancellation circuit synthesizes a phase synchronized cancellation pulse which is then injected onto the LIN driver output using an on-chip tunable capacitor array to cancel the switching noise injected via substrate. The proposed EMI reduction technique can track and cancel substrate noise independent of process technology and device parasitics, input voltage, duty cycle and loading conditions of the DC-DC switching regulator. The EMI cancellation system is designed and fabricated on a 180nm Bipolar-CMOS-DMOS (BCD) process with an integrated power stage of a DC-DC buck regulator at a switching frequency of 2MHz along with an automotive LIN driver. The EMI cancellation circuit occupies an area of 0.7 mm2, which is less than 3% of the overall area in a standard SBC and consumes 12.5 mW of power and achieves 25 dB reduction of conducted EMI in the LIN driver output’s power spectrum at the switching frequency and its harmonics.