Wearable ultrasound devices for imaging and therapeutic applications demand low-power and low-area integrated circuits to interface with ultrasound transducers. In the case of ultrasound imaging front-ends, discrete time-gain compensation (TGC) simplifies gain control in ultrasound imaging (USI) ASICs, but higher gain-step resolution increases area and power dissipation, while high PSRR is needed to suppress switching noise from co-integrated HV digital circuits. This work presents a programmable-gain floating inverter low-noise amplifier (FIALNA) architecture in 28nm CMOS for low-power, wide-bandwidth USI. A thermometer-encoded variable reservoir capacitance enables fine TGC with five PVT-robust gain steps, achieving 53.6dB PSRR and an area of 0.0023mm2, an order of magnitude smaller than current PGA designs. The FIALNA dissipates 116μW and achieves 59μVrms input-referred noise, making it suitable for low-power wearable ultrasound devices.

This work presents the design and simulation of a PVT-robust x16 gain dynamic open-loop inverter-based Gm-ratio residue-amplifier for high-speed SAR-assisted pipeline ADCs. The amplifier is designed in a 28 nm standard bulk CMOS process with a regulated 0.9 V power supply and simulated across a -20°C to 85°C temperature range. It achieves a power dissipation of 1.67 mW at 1.3 GHz, corresponding to a power-speed ratio of 1.28 mW/GHz, with less than ±5% gain variation throughout all temperature corners in typical conditions.

Most academic and commercial tri-dimensional (3D) parasitic resistance extraction EDA/CAD tools rely on finite element methods (FEM) and are mainly suited to digital circuitry. In analog and mixed-signal (AMS) circuits, such as power converters and radio-frequency analog front-ends, the layout structures used for the metal interconnections become much more diversified and complex. This paper proposes an EDA/CAD tool, based on an innovative methodology for 3D parasitic resistance extraction, leveraged by image processing techniques and algorithms. Some practical examples are shown to demonstrate the attractiveness of the proposed tool. Moreover, since our tool efficiently works in the domains of 2D image processing, if an extensive database of layouts is provided and enough training is carried out, advanced deep-learning techniques can be straightforwardly employed, speeding up parasitic resistance extraction in highly complex AMS layouts.

This paper reports a monolithic device integrating a CMOS analog front-end and an array of 192 MR sensors for biomolecular recognition detection. Innovative CMOS building blocks (i.e. current source, multiplexers and pre-amplifier) were designed targeting a negligible noise when compared with the MR sensors noise and a low power consumption. The CMOS front-end was fabricated using AMS 0.35 μm technology and the magnetoresistive sensors were post-fabricated on top of the CMOS chip. Due to its low noise (16 nV/√Hz), the full system was able to detect magnetic nanoparticles with a SNR degradation of only 1.4 dB (circuit imposed). Furthermore, the unprecedented low power consumption (6.5 mW) and small dimensions (7.59 mm2) of the presented solution guarantees the portability of the detection system allowing its usage at the point-of-care.

Non-destructive testing (NDT) based on eddy currents (EC) is commonly used to detect defects in conductive materials. Usually the system includes an emitter coil, and one receiver coil or one Magnetoresistive (MR) sensor. In this work we added an interface ASIC that pre-amplifies and filters the signal from an array of MR sensors. This demo will present a new version based on the work presented at the ECNDT 2014 conference with a paper entitled “A CMOS ASIC for Precise Reading of a Magnetoresistive Sensor Array for NDT”. Since this is an on-going work, improvements have been made, namely the reduction of the system thermal noise to 30 nV/√Hz, the development of a multigain amplifier and the application of the same concept and circuit to a multichannel parallel signal acquisition system. Detection of surface and buried defects will be demonstrated in different material mock-ups.