Demo Data from EDBT 2026 / reviewers in the wild / expert
Lingfeng Zhu
dblp:33/10848
· DBLP profile ↗
8ranked-venue papers
4as first author
3since 2021 · last 2025
—ORCID · conflict
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 3 · 2 first-author · 3 since 2021Applied, interdisciplinary, general and emerging computing · 3 · 2 first-authorGraphics, computer vision, multimedia, augmented reality and games · 2
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Electronic design automation · 100% | |
| Theoretical computer science
1 paper |
Automated reasoning and model checking · 100% |
Topics — the 4 heaviest of 4, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation › hardware verification and test
hardware verification |
0.9 | 1 | 2025 | Leveraging Critical Proof Obligations for Efficient IC3 Verification · DAC 2025 |
Electronic design automation › model checking
IC3 algorithm |
0.9 | 1 | 2025 | Leveraging Critical Proof Obligations for Efficient IC3 Verification · DAC 2025 |
Electronic design automation
model checking |
0.9 | 1 | 2025 | Leveraging Critical Proof Obligations for Efficient IC3 Verification · DAC 2025 |
Automated reasoning and model checking › model checking › symbolic model checking
SAT-based model checking |
0.3 | 1 | 2025 | Leveraging Critical Proof Obligations for Efficient IC3 Verification · DAC 2025 |
Methods — techniques the papers use, named apart from their topics
proof obligation propagation · 1.7UNSAT core generation · 1.7
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2025 | Leveraging Critical Proof Obligations for Efficient IC3 VerificationabstractIC3 and its variants are SAT-based model-checking methods that play a critical role in hardware verification. Efficient management of proof obligations, which track states that need to be proven unreachable, is essential for improving verification performance. This paper presents a novel approach that utilizes Critical Proof Obligations (CPOs) to improve proof obligation management. We propose two techniques, CPO-Driven UNSAT Core Generation and CPO-Driven Proof Obligation Propagation, to promote lemma propagation and frame refinement. Experimental results on HWMCC benchmarks demonstrate significant improvements in CPO discovery and lemma propagation, resulting in notable performance gains. Lingfeng Zhu, Xindi Zhang 0001, Shaowei Cai 0001 |
DAC | 1 |
| 2025 | A Three-Phase Fully-Integrated Reconfigurable Switched-Capacitor Converter For Near-Threshold ComputingabstractA fully-integrated reconfigurable switched-capacitor converter (SCC) that achieves very low voltage conversion ratios (1/4X, 1/5X and 1/6X) in a 65nm CMOS process is presented. It has three topological phases, and the SCC achieves minimum output resistance for every topology. An analysis is proposed to optimize the system efficiency with the consideration of charge redistribution loss, conduction loss, gate drive loss and bottomplate parasitic loss. Wing-Hung Ki, Junmin Jiang, Lingfeng Zhu, Yang Liu 0061 |
ISCAS | 4 |
| 2024 | D2 Buck Converter With Delay-Insensitive Response and Adaptive On-Time Extension During Load TransientabstractThis paper proposes a D2buck converter that achieves higher efficiency than the double-step-down (DSD) converter driving medium load current. It also minimizes undershoot and recovery time of load transient response. The D2buck converter consists of two buck converters in cascade, with the first handling high input voltage and low input current, and the second using low-voltage power switches to enhance efficiency. By implementing a sawtooth generator with well-defined thresholds, the undershoot detector realizes both delay-insensitive response and adaptive on-time extension during load transient. This work is designed in a 180nm BCD process. The first stage converts 24V to 4V, and the second stage converts 4V to 1V. For a load increase from 0.1A to 1.1A with an edge time of 20ns, the worst-case undershoot was better than 15%, and the recovery time was 2.7µs. The simulated peak efficiency was 91.9% with the load current ranging from 0.1A to 4A. Lingfeng Zhu, Wing-Hung Ki, Xiaofei Ma 0004, Junmin Jiang |
ISCAS | 1 |
| 2017 | Erratum to 'A shrinkage variable step size for normalized subband adaptive filters' SIGPRO 129C 2016, 56-61
Wei Xia 0003, Lingfeng Zhu, JuLei Zhu, Jinfeng Hu, Huiyong Li 0001 |
Signal Process. | 2 |
| 2016 | An enhanced mixed modulated Lagrange explicit time delay estimator with noisy inputabstractThe mixed modulated Lagrange explicit time delay estimation (MMLETDE) algorithm provides an efficient time delay estimation between narrowband or sinusoidal signals. However, it does not explicitly consider the additive measurement noise at the input, which actually exists in practice. Aiming at this issue, an enhanced MMLETDE algorithm is proposed for noisy inputs based on the unbiased impulse response estimation technique, assuming that the noise power ratio is known a priori. Simulation results show that for narrowband signals or sinusoids over a wide frequency range, the proposed algorithm with a small filter order performs well in moderate and high noise scenarios. Wei Xia 0003, JuLei Zhu, Wenying Jiang, Lingfeng Zhu |
Frontiers Inf. Technol. Electron. Eng. | 4 |
| 2016 | A shrinkage variable step size for normalized subband adaptive filters
Wei Xia 0003, Lingfeng Zhu, JuLei Zhu, Jinfeng Hu, Huiyong Li 0001 |
Signal Process. | 2 |
| 2003 | Study and implementation on parallel processing algorithm for DEPSabstractA study on efficient visualization and real-time interactivity of large-scale scenes is discussed. Introducing parallel processing technology, we present a parallelizable strategy with the pipeline algorithm, realize this parallel algorithm based on shared-memory, and then apply this program to a test site, the Peking Olympic Games planning mixed scenes, including real-time rendering, dynamical texture loading, quick browsing and so on. The results show a running performance and real-time interactivity improvement of DEPS (Digital Earth Prototype System) when using this algorithm. The parallel program of this paper was developed and running on a Silicon Graphics multiprocessor, Onyx 3200, with four MIPS R12000 processors and InfiniteReality 3 graphic accelerator, under IRIX 6.5 operating system. Lingfeng Zhu, Yun Shao 0001, Xiangtao Fan, Huadong Guo |
IGARSS | 1 |
| 2003 | Study on real-time simulation technology of large-scale virtual sceneabstractReal-time simulation technologies of a large-scale virtual scene are studied. Besides the building of LOD models (including terrain and cultural features) based on a viewpoint in the Peking Olympic Games Planning Regions as a demonstration area, we adopt Active Surface Definition, a real-time framework, to manage the terrain data, apply ClipTexture to manage the high-resolution textures efficiently, and utilize parallel processing technology to deploy the scene data dynamically, which result in higher fidelity and better simulation effects in the virtual scene we finally build up. Lingfeng Zhu, Yun Shao 0001, Xiangtao Fan, Huadong Guo |
IGARSS | 1 |