In this paper, disruptive research using generative diffusion models (DMs) with an attention-based encoder-decoder backbone is conducted to automate the sizing of analog integrated circuits (ICs). Unlike time-consuming optimization-based methods, the encoder-decoder DM is able to sample accurate solutions at push-button speed by solving the inverse sizing problem. Experimental results show that the proposed model outperforms the most recent deep learningbased techniques, presenting higher generalization capabilities to performance targets not seen during training.

This paper describes a course offered in the Master program in Electrical and Computer Engineering of Instituto Superior Tecnico, Universidade de Lisboa, and offered within the GreenChips-EDU platform. The course is on Ultra Low Power Circuits design. The novelty of this course is that the emphasis is on design of analog and digital circuits with CMOS technology using the transistors in subthreshold region, and less conventional low power topologies for RF circuits. The course uses professional CAD tools, currently "Cadence Design Framework II", and on production materials for the use of "Synopsys Custom Compiler", configured with a foundry technology design kit with precise modelling in all regions of operation of a MOS transistor. The design flow procedure is in accordance with common practices used in the industry. The proposed model has been classroom tested in the last three years with positive student reviews on course quality assessment.

This paper presents a performance-driven (PD) analog integrated circuit (IC) placement generator highly integrated with off-the-shelf tools, e.g., simulator, layout-versus-schematic and extractor, that promotes an exhaustive simulation-based synthesis. However, to bypass the timeconsuming extractions and simulations, novel post-layout performance regressors based on different highly accurate machine learning (ML) techniques are developed. The data used to train them can be directly and conveniently acquired from previous precise post-placement simulations. Experimental results show that a set of performance regressors based on extremely randomized trees (ERTs) operating on compressed design spaces allow to speed-up synthesis more than$20 \times$, which represents a step forward towards an efficient fully automatic PD analog IC design flow.

Integrated circuit design in millimeter-wave (mm-Wave) bands is exceptionally complex and dependent on costly electromagnetic (EM) simulations. Therefore, in the past few years, a growing interest has emerged in developing novel optimization-based methodologies for the automatic design of mm-Wave circuits. However, current approaches lack scalability when the circuit/system complexity increases. Besides, many also depend on EM simulators, which degrade their efficiency. This work resorts to hierarchical system partitioning and bottom-up design approaches, where a precise machine learning model - composed of hundreds of seamlessly integrated sub-models that guarantee high accuracy (validated against EM simulations and measurements) up to 200GHz - is embedded to design passive components, e.g., transformers and baluns. The model generates optimal design surfaces to be fed to the hierarchical levels above or acts as a performance estimator. With the proposed scheme, it is possible to remove the dependency of EM simulations during optimization. The proposed mixed-optimal-surface, performance estimator, and simulation-based bottom-up multiobjective optimization (MOO) are used to fully design a Ka-band mm-Wave transmitter from the device up to the system level in 65-nm CMOS for state-of-the-art specifications.

Low-noise amplifiers (LNAs) play a significant role in modern millimeter-wave (mmWave) integrated circuit multi-standard transceiver systems. This paper proposes a transformer-less LNA based on a cascade of two AC coupled common source stages, each with inductive degeneration, for the 28-GHz 5G communications band. An automatic design methodology explores the topology design space over a 148-dimensional performance space spreading through different corners for process, voltage, and temperature. It results in about 1000 optimized LNA variants, with gains achieving up to 17.5-dB, and the noise Figure and power consumption down to 2.4-dB and 1.86-mW, respectively. These performance figures position the adopted LNA’s performance boundaries with the most recent mmWave LNAs.

The automatic sizing of radio-frequency (RF) integrated circuit (IC) blocks in deep nanometer technologies has moved towards process, voltage, and temperature (PVT)-inclusive optimizations, to ensure their robustness. Each sizing solution is exhaustively simulated in a set of PVT corners, thus pushing modern workstations’ capabilities to their limits. This paper presents innovative research towards the automation of RF IC design by using deep learning to assist the simulation-based sizing tools in time-consuming PVT-inclusive optimizations. The proposed PVT regressor inputs the circuit’s sizing and the nominal performances to estimate the PVT corner performances via multiple parallel artificial neural networks. Two control phases prevent the optimization process from being misled by inaccurate performance estimates. The proposed controlled PVT estimator is tested on a state-of-the-art class C/D voltage-controlled oscillator, reducing the workload of the circuit simulator up to 79% while achieving a speed-up factor of $2.92 \times $, ultimately saving more than 16 days of computational effort.

The design of integrated circuits (ICs) in the analog spectrum is intricate due to the signals’ continuous nature. Additionally, it is strongly affected by the physical implementation of their devices on the circuits’ layout, a task that has stubbornly defied all automation attempts. In this paper, disruptive research using modern embedding techniques and a fully unsupervised attention-based encoder-decoder model is conducted to automate the placement task of analog IC layout design. The attention-based graph-to-sequence model, AGraph2Seq for short, differs from other heterogeneous graph embedding approaches by introducing structure in both the input and output data in an encoder-decoder architecture. The structure allows for a smaller and more effective placement regression model, drastically reducing the number of trainable parameters and turning the model inherently independent of the circuit topology in terms of the way devices are connected and the number of devices in a circuit, turning it easily scalable to circuits with higher complexity. Additionally, the attention mechanism makes the model’s decoder invariant to the input devices’ order. The deep model is ultimately trained in an end-to-end fashion to minimize a fully unsupervised loss function that efficiently evaluates the fulfillment of fundamental placement’s topological constraints. As a proof of concept, the final model, but also its intermediate stages, i.e., encoder-only, decoder-only, and encoder-decoder without attention, are extensively used to propose different placement solutions for several modern analog IC blocks in multiple deep nanometer technology nodes at push-button speed, including topologies not present in the training set. These present a level of generalization beyond traditional analog IC placement methodologies and most recent machine learning-based approaches and compete with or outperform highly optimized analog layouts and human-made designs.

In this paper, disruptive research using modern embedding techniques and an attention-based encoder-decoder deep learning (DL) model is conducted to automate analog layout synthesis. Unlike previous legacy-based placement automation mechanisms, the attention-based Graph2Seq model is inherently independent of the number of devices within a circuit topology and their order. Moreover, its unsupervised training does not rely on expensive legacy layout data but only on sizing solutions. Experimental results show that the proposed model generates placement solutions at push-button speed and can generalize to circuit topologies and technological nodes not used in training. Moreover, while being scalable, the model produces placement solutions that compete with highly optimized analog placements and other, order-dependent and non-scalable, DL models.

This paper presents an innovative approach toward the automation of the placement task of analog integrated circuit layout design by using an artificial neural network that generates multiple valid floorplan solutions at push-button speed. The proposed model extends the knowledge mining of the most recent layout generation techniques as an end-to-end approach. A novel loss function is used in a semi-supervised fashion for the model to learn how to generate effective placements that follow topological constraints instead of simply trying to copy devices' locations from some pre-existing labeled dataset of placement solutions. Thus, in addition to eliminating the need for a large dataset of placed sizing solutions for training, the model generalizes better and outputs better layouts for solutions outside the training set. Moreover, one step further is taken towards a model that can predict the placement of different circuit topologies by supporting different encodings (with different number of devices) on the input layer of the artificial neural networks, ultimately fostering an opportunity to reuse incomplete legacy layout information. As proof of concept, the one ANN trained for 2 amplifier topologies is used to produce multiple placement recommendations in less than 40 ms for new designs.

This paper presents fuzzy c-means-based yield estimation (FUZYE), a methodology that reduces the time impact caused by Monte Carlo (MC) simulations in the context of analog integrated circuits (ICs) yield estimation, enabling it for yield optimization with population-based algorithms, e.g., the genetic algorithm (GA). MC analysis is the most general and reliable technique for yield estimation, yet the considerable amount of time it requires has discouraged its adoption in population-based optimization tools. The proposed methodology reduces the total number of MC simulations that are required, since, at each GA generation, the population is clustered using a fuzzy c-means (FCMs) technique, and, only the representative individual (RI) from each cluster is subject to MC simulations. This paper shows that the yield for the rest of the population can be estimated based on the membership degree of FCM and RIs yield values alone. This new method was applied on two real circuit-sizing optimization problems and the obtained results were compared to the exhaustive approach, where all individuals of the population are subject to MC analysis. The FCM approach presents a reduction of 89% in the total number of MC simulations, when compared to the exhaustive MC analysis over the full population. Moreover, a k-means-based clustering algorithm was also tested and compared with the proposed FUZYE, with the latest showing an improvement up to 13% in yield estimation accuracy.

In this paper, an analysis of the methodologies proposed in the past years to automate the synthesis of radio-frequency (RF) integrated circuit blocks is presented. In the light of this analysis, and to avoid nonsystematic iterations between sizing and layout design steps, a multiobjective optimization-based layout-aware sizing approach with preoptimized integrated inductor(s) design space is proposed. An automatic layout generation from netlist to ready-to-fabricate prototype is carried in-the-loop for each tentative sizing solution using an RF-specific module generator, template-based placer and evolutionary multinet router with preoptimized interconnect widths. The proposed approach exploits the full capabilities of the most established computer-aided design tools for RF design available nowadays, i.e., RF circuit simulator as performance evaluator, electromagnetic simulator for inductor characterization, and layout extractor to determine the complete circuit layout parasitics. Experiments are conducted over a widely used circuit in the RF context, showing the advantages of performing complete layout-aware sizing optimization from the very initial stages of the design process.

In this paper, the performance boundaries and corresponding tradeoffs of a complex dual-mode class-C/D voltage-controlled oscillator (VCO) are extended using a framework for the automatic sizing of radio frequency integrated circuit blocks, where an all-inclusive test bench formulation enhanced with an additional measurement processing system enables the optimization of “everything at once” toward its true optimal tradeoffs. VCOs embedded in the state-of-the-art multistandard transceivers must comply with extremely high performance and ultralow power requirements for modern cellular and Internet of Things applications. However, the proper analysis of the design tradeoffs is tedious and impractical, as a large amount of conflicting performance figures obtained from multiple modes, test benches, and/or analysis must be considered simultaneously. Here, the dual-mode design and optimization conducted provided 287 design solutions with figures of merit above 192 dBc/Hz, where the power consumption varies from 0.134 to 1.333 mW, the phase noise at 10 MHz from -133.89 to -142.51 dBc/Hz, and the frequency pushing from 2 to 500 MHz/V, on the worst case of the tuning range. These results pushed this circuit design to its performance limits on a 65-nm CMOS technology, reducing 49% of the power consumption of the original design while also showing its potential for ultralow power with more than 93% reduction. In addition, worst case corner criteria were also performed on the top of the worst case tuning range optimization, taking the problem to a human-untrea table LXVI-D performance space.

State-of-the-art design of analog and radio frequency integrated circuits is often accomplished using sizing optimization. In this paper, an innovative combination of principal component analysis (PCA) and evolutionary computation is used to increase the optimizer's efficiency. The adopted NSGA-II optimization kernel is improved by applying the genetic operators of mutation and crossover on a transformed design-space, obtained from the latest set of solutions (the parents) using PCA. By applying crossover and mutation on variables that are projections of the principal components, the optimization moves more effectively, finding solutions with better performances, in the same amount of time, than the standard NSGA-II optimization kernel. The proposed method was validated in the optimization of two widely used analog circuits, an amplifier and a voltage controlled oscillator, reaching wider solutions sets, and in some cases, solutions sets that can be almost 3 times better in terms of hypervolume.

This paper presents the study and implementation of a new efficient yield optimization technique for multi-objective optimization-based automatic analog integrated circuit sizing. The approach uses a commercial electrical simulator and standard process design kit (PDK) models to perform, during the optimization process, the same Monte Carlo (MC) simulations that designers use. The proposed yield estimation technique reduces the number of required MC simulations by using the k-means algorithm, with a variable number of clusters, to select only a handful potential solutions where the MC simulations are performed. Due to the use of a commercial simulator tool and foundry supplied PDK models the developed methodology provides the most accurate and reliable results, and also, the variable k-means algorithm is able to achieve 91% reduction in the total number of the MC simulations required for an optimization, when considering MC simulations for all solutions. Moreover, this new approach presents a 50% increase in speed performance when comparing to a previous yield optimization technique also using k-means and MC simulations.

In this paper an innovative routing methodology considering wiring symmetry (WS) for multiport multiterminal (MP/MT) signal nets of analog and mixed-signal integrated circuits (ICs) is presented. In our work, first, an electromigration (EM)-aware wiring topology for each power and signal network is constructed directly from the netlist, and then, several embedded symmetry rules between wires are automatically identified and applied in the global and detailed routing phases. The use of such MP terminals strongly enhances both the ability to route the circuit and the WS. The design flow is demonstrated for the UMC 130nm design process.

This paper describes an electromigration-aware and IR-Drop avoidance routing approach considering multiport multiterminal (MP/MT) signal nets of analog integrated circuits (IC). The effects of current densities and temperature in the interconnects may cause the malfunction/failure of a circuit due to IR-Drop or electromigration (EM). These become increasingly more relevant with the ongoing reduction of circuit sizes caused by the evolution of the nanoscale integration processes. Therefore, EM and IR-Drop effects must be taken into account in the design of both power networks and signal wires of analog and mixed-signal ICs, to make their impact on the circuits' reliability negligible. In previous EM and IR-Drop-aware analog IC routing approaches, `dot-models' are assumed for the terminals, i.e., each terminal has only one port that need to be routed, however, in practice, analog standard cells usually contain multiple electrically-equivalent locations, often distributed over different fabrications layers, where legal connections can be made, i.e., MP terminals, which need to be properly explored. The design flow is detailed, and the applicability of the approach is demonstrated with experimental results, and also, by generating the routing of an analog circuit structure for the UMC 130 nm design process.

Typically the design of oscillators is done aiming at both minimum phase noise and minimum power consumption, however, these two objectives are contradictory. Yet, this tradeoff, which is also the base for the definition of the figure of merit of oscillators, is seldom explored is previous publications. In this paper, an LC-Voltage Controlled Oscillator (VCO) was considered in a multi-objective optimization process, where the accuracy and reliability of the solution is guaranteed by the usage of a circuit simulator to evaluate the circuit performance. The state-of-the-art circuit optimization tool AIDA-C was used in the automatic synthesis of the LC-VCO, obtaining a set of about 40 design solutions with FOM bellow -191 dBc/Hz, where the power consumption varies from 0.22 to 0.46 mW and the phase noise varies from -120.47 to -116.72 dBc/Hz.

In the state-of-the-art on analog integrated circuit (IC) automatic routing approaches it is assumed that each terminal has only one port that can be routed, however, in practice a device usually contains multiple electrically-equivalent locations where the connection can be made, multi-port terminals, which are not properly explored. This paper describes an innovative evolutionary approach with multi-port multiterminal (MP/MT) nets for analog IC automatic routing. The netlist and the multi-port terminals are modeled in a Group-Steiner problem that is solved by the Global Router, to obtain the terminal-to-terminal connectivity, and then, for the detailed routing, an optimization kernel is used, namely, an enhanced version of the multi-objective evolutionary algorithm NSGA-II. The Router starts by a single-net procedure, and culminates in a process where all nets are optimized simultaneously. The technology design rules are verified during the evolutionary generation using an in-loop built-in layout evaluation procedure. The automatic routing generation is detailed, and demonstrated for the generation of the layout of a typical analog circuit, for the UMC 130nm design process. The automatically generated layouts are validated using the industrial grade Calibre®tool and the performances of the extracted circuits are compared with the ones achieved in the circuit-level design.

This paper presents a new approach to enhance a state-of-the-art layout-aware analog IC circuit-level optimizer, by embedding statistical knowledge from an automatically generated gradient model into the multi-objective multi-constraint optimization kernel based on a modified NSGA-II algorithm. The gradient model is automatically generated by, first, using a design of experiments (DOE) approach with two alternative sampling strategies, the full factorial design and the fractional factorial design, which define the samples that will be accurately evaluated using a circuit simulator (e.g. HSPICE®), second, extracting and ranking the contributions of each design variable to each performance measure or objective, and, finally, building the model based on series of gradient rules. The gradient model is then embedded into the modified NSGA-II optimization kernel, by acting on the mutation operator. The approach was validated with typical analog circuit structures for an industry standard 0.13 μm integration process, showing that, by enhancing the circuit sizing evolutionary kernel with the gradient model, the optimal solutions are achieved, considerably, faster and with identical or superior accuracy.

This paper describes an innovative design automation tool, LAYGEN II, for analog integrated circuit (IC) layout generation based on template descriptions and on evolutionary computation techniques. LAYGEN II was developed giving special emphasis to the reusability of expert knowledge and to the efficiency of retargeting operations. The designer specifies the sized circuit-level structure, the required technology and also, the layout template consisting of technology and specification independent high-level layout guidelines. For placement, the topological relations present in the template are extracted to a nonslicing B*-tree layout representation, and the tool automatically merges devices and improves the floorplan quality. For routing an optimization kernel consisting of a tailored version of the multiobjective multiconstraint evolutionary algorithm NSGA-II is used. The Router optimizes all nets simultaneously and uses a built-in engine to evaluate each of the layout solutions. The automatic layout generation is demonstrated here using the LAYGEN II tool for typical analog circuit structures, and the results in GDSII format were validated using the industrial grade verification tool Calibre®.

This paper describes an innovative analog IC layout generation tool, LAYGEN II, based on evolutionary computation techniques. The designer provides the high level layout guidelines through an abstract layout template. The template contains placement and routing constrains independently from technology, and can be used hierarchically in the definition of templates for complex circuits. LAYGEN II uses this expert knowledge to guide the evolutionary optimization kernels during the automatic layout generation in the target technology. The routing task of the proceeding can range from a template-based approach to a full automatic generation, if only connectivity is provided. The LAYGEN II tool is demonstrated for the layout generation of two typical analog circuit structures and the results validated by Calibre® design rule check tool.