Despite significant advances in learning-based lossy compression algorithms, standardizing codecs remains a critical challenge. In this paper, we present the JPEG Processing Neural Operator (JPNeO), a next-generation JPEG algorithm that maintains full backward compatibility with the current JPEG format. Our JPNeO improves chroma component preservation and enhances reconstruction fidelity compared to existing artifact removal methods by incorporating neural operators in both the encoding and decoding stages. JPNeO achieves practical benefits in terms of reduced memory usage and parameter count. We further validate our hypothesis about the existence of a space with high mutual information through empirical evidence. In summary, the JPNeO functions as a high-performance out-of-the-box image compression pipeline without changing source coding's protocol. Our source code is available at https://github.com/WooKyoungHan/JPNeO.

Trendy suggestions for learning-based elastic warps enable the deep image stitchings to align images exposed to large parallax errors. Despite the remarkable alignments, the methods struggle with occasional holes or discontinuity between overlapping and non-overlapping regions of a target image as the applied training strategy mostly focuses on overlap region alignment. As a result, they require additional modules such as seam finder and image inpainting for hiding discontinuity and filling holes, respectively. In this work, we suggest Recurrent Elastic Warps (REwarp) that address the problem with Dirichlet boundary condition and boost performances by residual learning for recurrent misalign correction. Specifically, REwarp predicts a homography and a Thin-plate Spline (TPS) under the boundary constraint for discontinuity and hole-free image stitching. Our experiments show the favorable aligns and the competitive computational costs of REwarp compared to the existing stitching methods. Our source code is available at https://github.com/minshu-kim/REwarp.

Multipath and non-line-of-sight (NLOS) signals are the major causes of poor accuracy of a global navigation satellite system (GNSS) in urban areas. Despite the wide usage of the GNSS in populated urban areas, it is difficult to suggest a generalized method because multipath errors are user-specific and cannot be eliminated by the differential GNSS (DGNSS) or a real-time kinematic technique (RTK). This paper introduces a real-time multipath estimation and mitigation technique which considers compensation for the time offset between constellations. It also presents a mode-switching algorithm between the DGNSS and multipath mitigating mode and shows that this technique can be effectively utilized for automobiles in a deep urban environment without any help from sensors other than GNSS. The availability is improved from 64% to 100% and the error RMS is reduced from 11.1 m to 1.2 m on Teheran-ro, Seoul, Korea. Because this method does not require prior information or additional sensor implementation for high-positioning performance in deep urban areas, it is expected to gain wide usage in not only the automotive industry but also future intelligent transportation systems.

GNSS signals are easily blocked or degraded because of the dense presence of high-rise buildings in urban areas, and positioning errors arising from reflected signals amount to as much as hundreds of meters. Various conventional GNSS techniques have been utilized to resolve this problem, but applying them to urban environments has been difficult owing to the complexity of the reflected signals and their unpredictable and nonlinear variation to the signal receiving environments. In this study, multipath maps were generated for dynamic users at multiple positions on a road and a residual-based map selection algorithm was implemented to solve the problem of user position uncertainty in deep urban environments. GNSS data collected over a period of 327 min were used to train the multipath maps corresponding to 247 points near the 2.5 km stretch of the Teheran-ro road in Seoul, South Korea. The proposed system performed efficiently—it was verified to be capable of constructing a multipath map with a radius of 25 m using only 4 min of data. Moreover, it improved positioning accuracy by 45 % horizontally and by 80 % vertically, enabling the determination of the positional information of an urban vehicle with a horizontal accuracy of 18 m during 99% of the duration of a one-hour-long dynamic test. Due to the nonreliance of the proposed method on prior information or implementation of additional sensors, it is expected to be widely used for constructing map-based multipath mitigation models as part of intelligent transportation infrastructure in all cities in future.

We propose a novel haptic rendering scheme based on passive midpoint integrator (PMI), which is an extension of our prior non-iterative passive mechanical integrator (NPMI) to maximal coordinates for simulation of complex articulated rigid bodies and to multi-point intermittent contact with the linear complementarity problem (LCP) formulation incorporated. The proposed PMI-based haptic rendering then can stably simulate mechanical systems with wide-range of parameters/updaterates (in contrast to semi-implicit Euler integrator), while maintaining losslessness of simple harmonic oscillation (in contrast to implicit Euler integrator), as compared in this paper. Application of this PMI-based haptic rendering is also presented for multi-user virtual co-manipulation of shared rigid object in SE(3) using hand/fingers with multi-point contact over the Internet.

Efficient cache tag management is a primary design objective for large, in-package DRAM caches. Recently, Tagless DRAM Caches (TDCs) have been proposed to completely eliminate tagging structures from both on-die SRAM and in-package DRAM, which are a major scalability bottleneck for future multi-gigabyte DRAM caches. However, TDC imposes a constraint on DRAM cache block size to be the same as OS page size (e.g., 4KB) as it takes a unified approach to address translation and cache tag management. Caching at a page granularity, or page-based caching, incurs significant off-package DRAM bandwidth waste by over-fetching blocks within a page that are not actually used. Footprint caching is an effective solution to this problem, which fetches only those blocks that will likely be touched during the page's lifetime in the DRAM cache, referred to as the page's footprint. In this paper we demonstrate TDC opens up unique opportunities to realize efficient footprint caching with higher prediction accuracy and a lower hardware cost than the original footprint caching scheme. Since there are no cache tags in TDC, the footprints of cached pages are tracked at TLB, instead of cache tag array, to incur much lower on-die storage overhead than the original design. Besides, when a cached page is evicted, its footprint will be stored in the corresponding page table entry, instead of an auxiliary on-die structure (i.e., Footprint History Table), to prevent footprint thrashing among different pages, thus yielding higher accuracy in footprint prediction. The resulting design, called Footprint-augmented Tagless DRAM Cache (F-TDC), significantly improves the bandwidth efficiency of TDC, and hence its performance and energy efficiency. Our evaluation with 3D Through-Silicon-Via-based in-package DRAM demonstrates an average reduction of off-package bandwidth by 32.0%, which, in turn, improves IPC and EDP by 17.7% and 25.4%, respectively, over the state-of-the-art TDC with no footprint caching.

This paper introduces a tagless cache architecture for large in-package DRAM caches. The conventional die-stacked DRAM cache has both a TLB and a cache tag array, which are responsible for virtual-to-physical and physical-to-cache address translation, respectively. We propose to align the granularity of caching with OS page size and take a unified approach to address translation and cache tag management. To this end, we introduce cache-map TLB (cTLB), which stores virtual-to-cache, instead of virtual-to-physical, address mappings. At a TLB miss, the TLB miss handler allocates the requested block into the cache if it is not cached yet, and updates both the page table and cTLB with the virtual-to-cache address mapping. Assuming the availability of large in-package DRAM caches, this ensures that an access to the memory region within the TLB reach always hits in the cache with low hit latency since a TLB access immediately returns the exact location of the requested block in the cache, hence saving a tag-checking operation. The remaining cache space is used as victim cache for memory pages that are recently evicted from cTLB. By completely eliminating data structures for cache tag management, from either on-die SRAM or in-package DRAM, the proposed DRAM cache achieves best scalability and hit latency, while maintaining high hit rate of a fully associative cache. Our evaluation with 3D Through-Silicon Via (TSV)-based in-package DRAM demonstrates that the proposed cache improves the IPC and energy efficiency by 30.9% and 39.5%, respectively, compared to the baseline with no DRAM cache. These numbers translate to 4.3% and 23.8% improvements over an impractical SRAM-tag cache requiring megabytes of on-die SRAM storage, due to low hit latency and zero energy waste for cache tags.

Embedded DRAM (eDRAM) is becoming more and more popular as a low-cost alternative to on-chip SRAM. eDRAM is particularly attractive for frame buffers in video applications with ever increasing screen resolutions. However, eDRAM suffers short retention time and high refresh power, which prevents its widespread adoption. To save the refresh power of eDRAM-based frame buffers, we propose Tiered-Reliability Memory (TRM), where the frame buffer is divided into multiple segments with different refresh periods and hence different error rates. By allocating most-significant bits to the most reliable segment, our four-tier TRM reduces refresh power by 48% without degrading user experience.