A practical solution to the complexity of design validation is semi-formal verification, where the specification of correctness criteria is done formally, as in model checking, but checking is done using simulation, which is guided by directed vector sequences derived from knowledge of the design and/or the property being checked. Simulation vectors must be effective in targeting the types of bugs designers expect to find rather than some generic coverage metrics. The focus of our work is to generate property-specific testbenches for guided simulation, that are targeted either at proving the correctness of a full CTL property or at finding a bug. This is facilitated by generation of a property-specific model, called a "witness graph", which captures interesting paths in the design. Starting from an initial abstract model of the design, symbolic model checking, pruning, and refinement steps are applied in an iterative manner, until either a conclusive result is obtained or computing resources are exhausted. The witness graph is annotated with, e.g., state or transition priorities before testbench generation. The overall testbench generation flow, and the iterative flow for witness graph generation are shown.

In this paper, a tool to aid pipelined processor instruction set implementation is described.The purpose of the tool is to choose from among design alternatives a design that minimizes overall processor cost.In the proposed cost model processor cost has two components, the cost of hardware necessary to realize the processor and the cost of degraded performance due to pipeline hazards as compared to an ideal pipelined processor.The tool user provides several alternate hardware implementations of each instruction, the cost of hardware operators used, a trade-off factor representing the relative importance of hardware cost versus degraded performance cost, and a straight line benchmark program which is used by the tool to determine frequency of occurrence of pairs of instructions.Using a linear programming approach, the tool selects an implementation for each instruction which gives an overall cost which is optimal.

A method of tree-height minimization of networks of commutative and associative operators is described. The algorithm aims at minimizing latency and shimming delays in a synchronous data flow architecture such as that used in bit/digit-serial computation. The algorithm rearranges adder/subtractor trees to meet the joint goals, often allowing otherwise impossible scheduling constraints to be met. The algorithmic methods are found to apply also to trees of adders and shifters, such as those found in shift/add multipliers.>

We present an algorithm for automating the choice of operator configurations while synthesizing a pipelined design. The chosen configuration set must meet the design constraints of the pipeline (number of stages and stage time) while minimizing the total cost(s) (e.g. area, power) of the design. The configuration algorithm is first used with heuristics to make initial operator choices for insertion of stage latches; then optimally to choose configurations within each stage. Some advantages to this new algorithm are that it will allow the designer to specify both the number of stages as well as the latency of each stage, and that it will take arbitrary timing functions.

A method of tree-height minimization for networks of commutative and associative operators is proposed. An algorithm is described for minimizing latency and shimming delays in a synchronous data-flow architecture such as that used in pipelined or bit- or digit-serial computation. The algorithm rearranges operator trees to meet the joint goals, often allowing otherwise impossible scheduling constraints to be met. It may also be applied to word-parallel pipelined architectures to optimize operator trees within pipelined stages. The method is evaluated by testing it on several filter examples for which it finds optimal network topologies and schedules.>

A scheduling and hardware sharing algorithm is presented. This algorithm is generic and can be used for synthesizing both nonpipelined and pipelined data paths. The scheduling algorithm tries to distribute operations equally among partitions to maximize hardware sharing. Multiplexer delays are explicitly considered to produce a more accurate scheduling. In hardware sharing, structural parameters such as the size of multiplexers, interconnect overhead, the size of the smallest sharable operator etc. are used to control the amount of sharing globally and produce a heuristically optimized RTL structure. The scheduling algorithm is iterated until a satisfactory structure is obtained. The algorithm also can be used for partitioning a large system into implementable pieces. The algorithm has been used successfully for synthesizing a pipelined data path from a graphics processing description that contains about 1000 components.>

A conditional resource-sharing algorithm for pipeline synthesis is presented. It allows sharing of hardware components among the mutually exclusive parts of any conditional branches appearing in a behavioral description. If done improperly, resource sharing in a conditional branch can increase its critical path delay excessively, causing performance degradation. Given area/time constraints for a pipelined design, finding an optimal conditional sharing solution is a combinatorial optimization problem. The algorithm uses heuristics with a user-defined weight that trades off area versus time; the algorithm is either manually or automatically iterated by changing the weight until a solution close to the target is obtained or is determined to be impossible to obtain. The algorithm is interactive, so designers can manually determine partial or whole sharing.>

A design automation system for the design of digital systems from a high-level algorithmic description is proposed. The definition of the data-dependence graph and techniques for performing transformations that lead to optimization of hardware are described. The system can be used on several levels of design with the VLSI layout level given particular emphasis.