Qiuyang Wu

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EDBT 2026 Demo / reviewers in the wild / expert

dblp:33/245 · DBLP profile ↗

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3ranked-venue papers

1as first author

0since 2021 · last 2016

—ORCID · unresolved

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2Artificial intelligence and machine learning · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems

1 paper

Electronic design automation · 100%

Topics — the 5 heaviest of 5, each with the papers that count most for it

Topic	Papers	Last	Evidence papers
Electronic design automation design flow	1	2002	Automated timing model generation · DAC 2002
Electronic design automation › design methodology hierarchical design	1	2002	Automated timing model generation · DAC 2002
Electronic design automation › system-level design IP reuse	1	2002	Automated timing model generation · DAC 2002
Electronic design automation timing analysis	1	2002	Automated timing model generation · DAC 2002
Electronic design automation timing model generation	1	2002	Automated timing model generation · DAC 2002

Methods — techniques the papers use, named apart from their topics

static timing analysis · 0.0

Year	Publication	Venue	Position
2016	Histone modification patterns in highly differentiation cells Qiuyang Wu, Jihong Guan, Shuigeng Zhou	Neurocomputing	1
2013	To do or not to do hierarchical timing? abstract The latest design specs have arrived and it is now clear that timing runs will not fit in our machines. What to do! Is hierarchical STA the perfect solution? Will it work exactly like flat? How will it interact with the hierarchical design implementation? This talk will present the advantages and limitations of using hierarchical STA and how it impacts the design process. Florentin Dartu, Qiuyang Wu	ISPD	2
2002	Automated timing model generation abstract The automated generation of timing models from gate-level netlists facilitates IP reuse and dramatically improves chip-level STA runtime in a hierarchical design flow. In this paper we discuss two different approaches to model generation, the design flows they lend themselves to and results from the application of these model generation solutions to large customer designs. Ajay J. Daga, Loa Mize, Subramanyam Sripada, Chris Wolff, Qiuyang Wu	DAC	5