Structured ASICs have recently emerged as an exciting alternative to ASIC or FPGA design style as they provide a new trade-off between the high performance of ASIC design and low non-recurring engineering (NRE) costs of FPGA design. To fully utilize the benefits of structured ASICs, key physical design stage like placement should be made aware of modularity of their architecture. In this work, we propose a novel solution to placement for structured ASICs. In particular, we propose creation of intermediate virtual platform to exploit the regularity of structured ASIC and Integer Linear Program and network flow formulations for satisfying constraints associated with typical structured ASIC clock architectures. A preliminary version of this work recently won the structured ASIC placement contest by eASIC [1]. Our placer achieves 35% and 5% wirelength improvement over other placers and can place a design of 1 million cells in approximately 4 hours.