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Thomas-Rolf Banniza

dblp:33/295 · DBLP profile ↗
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3ranked-venue papers
1as first author
0since 2021 · last 2012
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Computer networks · 3 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Integrated circuit design · 44% Interconnection networks and networks-on-chip · 44% Distributed systems · 13%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Interconnection networks and networks-on-chip › switch architecture
self-routing switch
0.011991
Design and Technology Aspects of VLSI's for ATM Switches · IEEE J. Sel. Areas Commun. 1991
Integrated circuit design
VLSI design
0.011991
Design and Technology Aspects of VLSI's for ATM Switches · IEEE J. Sel. Areas Commun. 1991
Distributed systems
fault tolerance
0.011991
Design and Technology Aspects of VLSI's for ATM Switches · IEEE J. Sel. Areas Commun. 1991

Methods — techniques the papers use, named apart from their topics

shared buffer memory · 0.0logic simulation · 0.0hardware description language · 0.0
YearPublicationVenuePosition
2012 Performance comparison of scheduling algorithms for multipath transfer
abstract
Multipath transport protocols such as Multipath TCP can concurrently use several subflows to transmit a TCP flow over potentially different paths. Since more than one subflow is used, an efficient multipath scheduling algorithm is needed at the sender. The objective of the scheduler is to identify the subflow over which the current data packet should be sent. This paper compares the most important types of schedulers for multipath transfers. We model their performance analytically and derive key metrics, most notably the resulting end-to-end delay over heterogeneous paths. Our results show that a scheduler minimizing the packet delivery delay yields the best overall performance, but it is complex to realize. An alternative scheduler based on the sender queue size is simpler and has sufficient performance for relatively small asymmetry between the multiple paths. Our model results are confirmed by measurements with a real multipath transport protocol.
Amanpreet Singh, Carmelita Görg, Andreas Timm-Giel, Michael Scharf, Thomas-Rolf Banniza
GLOBECOM5
2011 MCTCP: A Multipath Transport Shim Layer
abstract
Multipath transport protocols enable the concurrent use of different paths and resource pooling of their capacity. Ongoing research and standardization activities extend the Transmission Control Protocol (TCP) towards a Multipath TCP solution. The objective is to aggregate multiple subflows between two endpoints into a single session that can be accessed by an application like a single TCP connection. This paper presents and evaluates Multi-Connection TCP (MCTCP) as a new multipath transport solution. MCTCP consists of a shim layer on top of several TCP connections and encodes control information, as far as possible, in their payload. In this paper, we first motivate MCTCP's design and compare it to a multipath transport protocol that uses TCP option encoding only. Second, we show that MCTCP can be implemented in the Linux stack with very few kernel modifications. We also demonstrate that MCTCP can be combined with a coupled multipath congestion control mechanism. Measurement results prove that MCTCP is an efficient and robust protocol that can dynamicall.y pool the bandwidth of several paths.
Michael Scharf, Thomas-Rolf Banniza
GLOBECOM2
1991 Design and Technology Aspects of VLSI's for ATM Switches
abstract
A system concept based on a multipath self-routing switching principle and on an internal transfer mode using multislot cells is introduced. With the utilization of a shared buffer memory structure, this concept allows for a single-chip realization of the switching elements and fulfils important system requirements like fault tolerance, independence of the switch core from external data formats and traffic characteristics, and modular extendibility from small to very large systems. An example implementation of the concept with the resulting functional partitioning in boards and chips is given. Performance study results, as a basis for dimensioning, are also presented. The most important design aspects and a possible tool chain exploiting a hardware description language, logic simulator, and logic compiler are highlighted.>
Thomas-Rolf Banniza, Gert J. Eilenberger, Bart Pauwels, Yves Therasse
IEEE J. Sel. Areas Commun.1