For an all-digital phase-locked loop, the frequency range supported is often segmented, and this could cause significant jitter when the operating condition (such as the supply voltage and/or the temperature) changes. To address this issue, we present a scheme, called smooth code-jumping, that can stitch together the segmented frequency profile of a digitally controlled oscillator (DCO) into a continuous range, and thereby reduce the jitter significantly. This scheme incorporates a new mirror-DCO-based calibration scheme to take into account process variations. We validate this scheme by test chips in 0.18-μm CMOS technology. Measurement results show that, when operating at 1 GHz, the rms jitter is 4.3 ps (0.43%UI) and the peak-to-peak jitter is 35.6 ps (3.56%UI), respectively.

In this paper, we introduce an integrated power methodology for multi-core SoC designs. It features not only a bottom-up IP-based power modeling for all kinds of IP components ranging from hardware accelerators, processors, and memory blocks, but also a top-down system-wide ESL power estimation formulation. By linking these two methods of different levels of abstraction, one can thereby easily profile the power consumption of a multi-core SoC running a complete application while retaining high accuracy of estimation. We have realized the proposed methodology into two software tools: (1) PowerMixerIP, an IP-based power model builder that uses different strategies to build versatile power models for general IPs and processor IPs, and (2) PowerDepot, an ESL power estimation tool that can interact with the users in a simple way and then generate the needed power monitors to be embedded into the ESL design in SystemC for super-fast power estimation so as to facilitate early-stage system-wide power profiling. The application of these tools on a dual-core real-life designs executing an H. 264 shows that the average error of the ESL power estimation is less than 2%, while the speedup can be up to 2400X when comparing to gate-level simulation.

In this paper, we present an automatic leakage power modeling method for standard cell library as well as SRAM compiler. For this problem, there are two major challenges - (1) the high sensitivity of leakage power to the temperature (e.g., the leakage power of an inverter can be different by 19.28X when temperature rises from 25°C to 100°C in 90nm technology), and (2) the large number of models to be built (e.g., there could be 80,835 SRAM macros supported by an SRAM compiler). Our method achieves high accuracy efficiently by two formula-based prediction techniques. First of all, we incorporate a quick segmented exponential interpolation scheme to take into account the effects of the temperature. Secondly, we use a MUX-oriented linear extrapolation scheme, which is so accurate that it allows us to build the leakage power models for all SRAM macros based on linear regression using only the simulation results of 9 small-sized SRAM macros. Experimental results show that this method is not only accurate but also highly efficient.

We present a vector selection methodology for estimating the peak power dissipation in a CMOS logic circuit. The ultimate goal is to combine the speed of RT-level simulation with the accuracy of low-level power simulation. We rely on efficient RT-level peak power prediction heuristics to select a handful of input vector pairs from the simulation testbench. These vector pairs are highly likely to induce the worst-case peak power. After that, the low-level power simulation is performed only with these peak power candidate vector pairs to obtain the realistic peak power values. Computationally, there are three major stages in our methodology. Firstly, we analyze the structure of the circuit and calculate the peak power weight for each input pin so as to construct a so-called mountain-based model. Secondly, we perform waveform composition to compute the peak power metric for each given input vector pair. Finally, we select a few candidate vectors for low-level power simulation. By doing so, the time-consuming simulation at the low levels can be mostly avoided without losing accuracy. Experiment results show that only less than 1% of the total functional patterns defined in a testbench are needed to be selected for low-level power simulation in order to catch the worst-case peak power vector pair.