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Krishna Bharath

dblp:33/3459 · DBLP profile ↗
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4ranked-venue papers
2as first author
0since 2021 · last 2008
0000-0002-6024-2402ORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 4 · 2 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
3 papers
Electronic design automation · 78% Integrated circuit design · 22%

Topics — the 5 heaviest of 6, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Integrated circuit design › packaging
system-in-package
0.122007
System level signal and power integrity analysis methodology for system-in-package applications · DAC 2006
Computationally Efficient Power Integrity Simulation for System-on-Package Applications · DAC 2007
Electronic design automation › physical design
power delivery network design
0.112008
Automatic package and board decoupling capacitor placement using genetic algorithms and M-FDM · DAC 2008
Electronic design automation › power integrity
power integrity analysis
0.112006
System level signal and power integrity analysis methodology for system-in-package applications · DAC 2006
Electronic design automation
signal integrity
0.112006
System level signal and power integrity analysis methodology for system-in-package applications · DAC 2006
Electronic design automation
power integrity
0.012008
Automatic package and board decoupling capacitor placement using genetic algorithms and M-FDM · DAC 2008

Methods — techniques the papers use, named apart from their topics

multi-layer finite difference method · 0.2genetic algorithm · 0.1modeling and simulation · 0.1
YearPublicationVenuePosition
2008 Automatic package and board decoupling capacitor placement using genetic algorithms and M-FDM
abstract
In the design of complex power distribution networks (PDN) with multiple power islands, it is required that the PDN represents a low impedance as seen by the digital modules. This is to reduce the simultaneous switching noise (SSN), generated due to the switching activity of digital drivers. Typically this reduction in impedance is accomplished by placing decoupling capacitors between the power and ground planes of a package or board. However, the performance of the decoupling solution is a function of capacitor selection and its placement. In this paper, an automatic capacitor placement optimization method has been proposed. This method relies on a genetic algorithm to provide a stochastic search of the design space, while employing an efficient core PDN simulator based on the multi-layer finite difference method (M-FDM). The technique has been employed to show optimized placements for split planes as well as for a realistic multi-layer server board.
Krishna Bharath, Ege Engin, Madhavan Swaminathan
DAC1
2007 Computationally Efficient Power Integrity Simulation for System-on-Package Applications
abstract
Power integrity simulation for system-on-package (SoP) based modules is a crucial bottleneck in the SoP design flow. In this paper, the multi-layer finite difference method (M-FDM) augmented with models for split planes has been proposed as a fast and accurate frequency domain engine. Results demonstrating the accuracy and scalability of the method have been presented. In particular, the algorithm was employed to the analysis of a realistic 6 layer package with ~ 200k nodes.
Krishna Bharath, Ege Engin, Madhavan Swaminathan, Kazuhide Uriu, Toru Yamada
DAC1
2007 Analysis for Signal and Power Integrity Using the Multilayered Finite Difference Method
abstract
We present a method for fast analysis of signal and power integrity based on a recently developed multilayered finite difference method (M-FDM). In order to accurately model multilayered planar structures, which are three dimensional, M-FDM combines two-dimensional models for power/ground planes using a multilayered unit cell approach. In this way, noise coupling can be considered not only in the transversal direction between two planes, but also vertically from one plane pair to another through the apertures and via holes. For a cosimulation of signal and power integrity, transmission line models also need to be included. The interaction between the signal transmission and power distribution modes is taken into account using a modal decomposition technique. An equivalent circuit model becomes available based on this finite difference approximation as well. Based on this network representation, second order effects such as fringe and gap fields can be included in M-FDM using equivalent circuit models for these fields. This results in a very accurate method that can be used for fast analysis of signal and power integrity in arbitrary package and board designs having any stack-up configuration and number of layers.
Ege Engin, Krishna Bharath, Madhavan Swaminathan
ISCAS2
2006 System level signal and power integrity analysis methodology for system-in-package applications
abstract
This paper describes a methodology for performing system level signal and power integrity analyses of SiP-based systems. The paper briefly outlines some new modeling and simulation techniques that have been developed to enable the proposed methodology. Some results based on the application of this methodology on test systems are also presented.
Rohan Mandrekar, Krishna Bharath, Krishna Srinivasan, Ege Engin, Madhavan Swaminathan
DAC2