This paper presents a pulse-modulated Class-E RF digital power amplifier (DPA) operating in the 1.4 GHz to 1.9 GHz frequency range, targeting GNSS and NB-IoT frequency bands. The proposed DPA achieves a saturated output power (Psat) of 24.2 dBm and a peak power-added efficiency (PAE) of 40% with the DPA core occupying 0.56mm2. It supports the transmission of GMSK, BPSK, π/4-DQPSK and QPSK modulated signals using a polar transmitter configuration. The pulse modulation approach enhances average power efficiency, delivering an average PAE of 37.7% with an error vector magnitude (EVM) of 0.7% for GMSK signals at a data rate of 30 Msymbols/s. For π/4-DQPSK signals at the same data rate, the DPA achieves an average PAE of 36.7% and an EVM of 7.7%. With the integration of a power combiner, the output power dynamic range can be extended by 9.2 dB while the average PAE of the proposed design outperforms by 4% the conventional Class-E RF PA. The chip is fabricated using GlobalFoundries’ 22nm FD-SOI CMOS technology (GF22FDX).

For decades, the terahertz (THz) frequency band had been primarily explored in the context of radar, imaging, and spectroscopy, where multi-gigahertz (GHz) and even THz-wide channels and the properties of THz photons offered attractive target accuracy, resolution, and classification capabilities. Meanwhile, the exploitation of the THz band for wireless communication had originally been limited due to several reasons:1) no immediate need for such high data rates available via THz bands and 2) challenges in designing sufficiently high-power THz systems at reasonable cost and efficiency, leading to what was often referred to as “the THz gap.” Over the recent decade, advances on many fronts have drastically changed the THz landscape. First, the evolution from 5G-to 6G-grade wireless systems dictates the need to support novel bandwidth-hungry applications and services for both data transfer i.e., eXtended Reality (XR), the Metaverse, and vast modeling needs of artificial intelligence (AI) and machine learning (ML), as well as centimeter-precision sensing and classification (i.e., for standalone position location, vehicle-to-everything (V2X), or unmanned aerial vehicle (UAV) tracking). Second, substantial progress in THz hardware has been achieved, offering promise that the THz technology gap will be closed. Hence, THz-band wireless communication seems inevitably an essential part of the future networking technology landscape in the coming decades. To design efficient THz systems, the peculiarities of THz hardware and THz channels need to be understood and accounted for. This roadmap paper first reviews the evolution of the hardware design approaches for THz systems, including electronic, photonic, and plasmonic approaches, and the understanding of the THz channel itself, in diverse scenarios, ranging from common indoors and outdoors scenarios to intrabody and outer space environments. This article then summarizes the lessons learned during this multidecade process and the cutting-edge state-of-the-art findings, including novel methods to quantify power efficiency, which will become more important in making design choices. Finally, this article presents the authors’ perspective and insights on how the evolution of THz systems design will continue toward enabling efficient THz communications and sensing solutions as an integral part of next-generation wireless systems.

This paper presents a non-Hermitian physics-inspired voltage-controlled oscillator (VCO) topology, which is termed parity-time-symmetric topology. The VCO consists of two coupled inductor-capacitor (LC) cores with a balanced gain and loss profile. Due to the interplay between the gain/loss and their coupling, an extra degree of freedom is enabled via resistive tuning, which can enhance the frequency tuning range (FTR) beyond the bounds of conventional capacitive or inductive tuning. A silicon prototype is implemented in a standard 130 nm bulk CMOS process with a core area of$0.15\mathbf{mm}^{2}$. Experimental results show that it achieves a$3.1\times$FTR improvement and 30% phase noise reduction of the baseline VCO with the same amount of capacitive tuning ability.

This article presents a differential vector modulatorbased phase rotator (PR) performing 360° full-span phase interpolation over a first-ever decade-wide instantaneous bandwidth from 2 to 24 GHz. The proposed PR employs a three-stage transformer poly-phase network with high-precision and ultrawide-bandwidth, two highly linear 5-bit variable gain amplifiers (VGAs), a differential series-shunt-series inductor peaking load network for bandwidth extension and an open-drain buffer. It is implemented in a standard 65-nm bulk CMOS process with a chip area of 1.2 mm x 1.8 mm. The measurement results demonstrate the maximum rms quantization phase error of 1.22° within a 1.5-dB output magnitude variation for full 360° interpolations from 2 to 24 GHz and the -3-dB magnitude bandwidth is up to 19 GHz, respectively. Moreover, due to the wideband high-quality in-phase/quadrature (I/Q) signal generation and high-precision I/Q interpolation of the VGAs, the PR can perform full-span phase synthesis with a constant set of phase shift code settings for all the operating frequencies. For interpolating 22.5°/15° phase step over the 360° full-span, the “one-code” setting operation achieves an rms phase error of 1.56°/1.42° from 3.5 to 22.5 GHz without any frequency-dependent code/look-up table (LUT), tunable element, or band-selection switch. Furthermore, with the “one-code” setting operation, the modulation tests demonstrate measured rms error-vector-magnitude (EVM) values below 5% for a 50-kSym/s QPSK signal from 3.3 to 22.3 GHz and for a 16-quadratic-amplitude modulation (QAM) signal from 2.7 to 22 GHz.

A novel highly-efficient multi-band multi-mode all digital quadrature transmitter is presented. The all digital transmitter uses in-phase (I) codeword and quadrature (Q) codeword to control a switching-mode power amplifier (PA) or digital PA (DPA) consisting of in-phase PA (I-PA) and quadrature PA (Q-PA), where each of the power cells inside I-PA or Q-PA is either on or off. Due to the load interaction between I-PA and Q-PA, a 2-dimensional digital pre-distortion is applied to linearize DPA. The total transmitter is implemented in 40nm CMOS LP process and occupies a die area of 0.7mm2. The digital quadrature transmitter can support 20MHz, 40MHz, and 80MHz WiFi signals, Band 38 and Band 40 LTE signals with class 3 output power, and Bluetooth BDR, EDR2, and EDR3 signals.