Silicon photonic networks are revolutionizing computing systems by improving the energy efficiency, bandwidth, and latency of data movements. Optical modulators, such as microresonators (MRs) and Mach–Zehnder interferometers (MZIs), are the basic building blocks of silicon photonic networks. This paper proposes a SPICE-compatible electro-optical co-simulation model, basic optical switch integration model (BOSIM), to systematically study optical modulators using PN, PIN, and metal–insulator–silicon (MIS) capacitor device technologies. BOSIM holistically models both transient and steady state properties, such as switching speed, power, transmission spectrum, area, and carrier distribution. BOSIM is validated by the measured data from eight research groups and companies. Compared to MRs, BOSIM shows MZIs are fast, with a high extinction ratio and large bandwidth but in the sacrifice of loss, energy, and area. Using a PIN diode over a PN diode can save area, but retain the loss and energy, while an MIS capacitor has the shock response of carrier distribution in a narrow range and is marginalized gradually. For instance, an MZI can achieve a$2.5 {\times }$bit rate,$6.06{\times }$extinction ratio,$71.04 {\times }\,\,3$-dB bandwidth, but costs at least$1.93 {\times }$passing loss,$1.46 {\times }$energy consumption, and$16.67 {\times }$area, compared with MR.

While many new applications prefer manycore processor with a large number of cores, the exploding communications among multiple cores, caches, and off-chip memories is posing a fundamental challenge on manycore designs. Silicon photonics-based interconnection network promises high bandwidth, low latency, and high energy efficiency, and can potentially meet the communication requirements of manycore processors. In this paper, we propose CAMON, a small low-cost silicon photonic chiplet integrated into the manycore processor package. CAMON chiplet can effectively alleviate the communication bottlenecks of manycore processors and improve the energy efficiency of data movement, especially for large-scale systems. We develop a distributed arbitration system, a low-power low-latency optical interface, and an off-chip laser preactivation mechanism for CAMON. The experimental results show that compared with the electrical network, CAMON can improve the full-system performance per energy by 4.6×, speedup the manycore processor by 2.7×, and save the area of the processor die by 3%, in a 512-core system.

The advancement of silicon photonics promises integrated optical switches to provide high-bandwidth, low-latency, and low-power communications in data centers. An optical switch’s loss limits its scale and affects the energy efficiency of the switch system. In this paper, we present cross-layer optical switch optimization (CLOSO), a cross-layer optimization (CLO) framework, based on not only photonic device models at the physical layer but also optical switch models at the fabric layer. With the proposed framework, optimal losses of optical switches can be evaluated efficiently, and the corresponding losses and design parameters of photonic devices can be obtained. Using CLOSO, we optimize four categories of integrated optical switches, Crossbar, PILOSS, DRAGON, and FODON, and compare them regarding their optimal worst-case loss with variation of the switch scale and data rate of signals. Furthermore, system-level evaluations of the optimized optical switches are performed, demonstrating a significant improvement of energy efficiency from the CLO. For instance, CLOSO helps to reduce the energy consumption of a 64-port DRAGON and FODON to as low as 6 pJ/bit and that of a 128-port DRAGON and FODON to as low as 10 pJ/bit. The investigation of 128-port switches also shows the necessity of adaptive power control on lasers for high-radix integrated optical switches. Through quantitative analyses and comparisons, CLOSO shows the capability of facilitating initial design exploration of optical switches and paves the way to fair evaluations and comparisons of switch systems in data centers.

Rack-scale computing systems are promising to undertake the emerging large-scale applications by distributing massive tasks to processing cores. The communication and coordination efficiency of these tasks and resources directly affect the system performance and energy consumption. Silicon photonic interconnects are expected to address the communication and system power consumption challenges imposed on rack-scale systems. However, the control for optical interconnects can cause server performance degradation if not properly designed, especially for the complicated and time-consuming multidomain networks. In this paper, we study the optical interconnects for rack-scale computing systems and propose a new communication flow and control scheme for the efficient coordination of distributed resources. Particularly, we first propose a forward propagation strategy that parallels the path reservation process with the distributed tasks connection setup. Second, we develop a pre-emptive chain feedback (PCF) scheme to optimize multidomain path reservation. The PCF scheme pre-emptively allocates network resources with the help of multicell reservation window and quickly releases resources with a feedback mechanism. This solution increases the network resources utilization and task coordination efficiency while minimizing path reservation overheads. Comparing to the baseline InfiniBand network fabric and handshake scheme, PCF can improve network throughput greatly under uniform and hotspot traffic patterns. Realistic benchmark results show that the PCF scheme on average reduces 52% and 60% energy consumption per unit system performance than InfiniBand and the handshake scheme for a 256-node rack system.

In recent years, optical interconnection networks have been proposed in order to achieve the ultrahigh bandwidth and low latency requirements for inter/intra-chip communication. In these optical interconection networks, series of basic optical elements are employed. Via these series of optical elements, the intrinsic crosstalk noise is generated. With a large scale of these optical elements, the signal-to-noise ratio (SNR) of an optical interconnect can be reduced by this crosstalk noise. In this paper, we utilize the adaptive power control (APC) to enhance the SNR under the crosstalk noise constraints. APC has been known to save energy and reduce power consumption. We apply this technique in one of the inter/intra-chip optical interconnect called I2CON. A new cluster design, namely the Beam cluster, is also introduced. Results have demonstrated that the APC can help to reduce crosstalk noise, hence, the overall SNR is improved. Comparison results have also indicated the further improvement of SNR in I2CON using Beam cluster when APC is applied.

In this paper, we propose an approach to accelerate path delay fault simulation of long test sequences. Several key ideas, namely judicious selection of path delay faults to be simulated, extraction of a compact set of necessary conditions to detect selected faults at primary inputs, and an on-demand selective simulation of input vectors based on their satisfaction of these necessary conditions, are proposed. We demonstrate the benefits of our methodology via experiments on benchmark circuits, with one large test case (S9234) showing a 114X speed-up over a traditional approach.

Sticky path-delay faults are path delay faults that are neither robustly nor non-robustly testable, but cannot be proven functionally unsensitizable. Better characterization of delay test quality requires a proper analysis of sticky path-delay faults. Furthermore, careful elimination of sticky path-delay faults contributes significantly to test development productivity and reduction of delay test cost. We present an industrial case study that shows the following, (a) On average, even after designers have removed false paths using automated tools and manual overrides, about 8% of path-delay faults with slack less than 10% of the clock period can be sticky, (b) Our approach, which extends a previously proposed technique, identifies a large subset of sticky path-delay faults that cannot cause functional failures and hence can be eliminated from further consideration. This significantly refines the delay test quality assessment and test development effort, (c) Our approach significantly reprioritizes (reorders) the remaining paths for test generation thereby improving the quality of the target path list.

This paper presents a study of the implication based functional constraint extraction techniques to generate pseudo functional scan tests. Novel algorithms to extract pair-wise and multi-node constraints as Boolean expressions on arbitrary gates in the design are presented. Its impact on reducing the overkill in testing was analyzed, and report the trade-offs in coverage and scan-loads for a number of fault models. In the case of path-delay fault model, it was shown that the longest paths contribute most to the over-testing problem, raising the question about scan testing of the longest paths. Finally, the evaluation of the functional constraints on large industrial circuits show that the proposed constraint generation algorithm generate a powerful set of constraints most of which are not captured in the constraints extracted by designers for design-verification purposes

Silicon evaluation of scan patterns, targeting realistic bridges, for a high performance microprocessor is presented. The practicality of generating realistic bridge patterns is demonstrated. Silicon data, with and without functional fails, and in the presence of n-detect tests are presented. Data points to the value of and efficiency of bridge patterns. Data also shows the advantage of using supplemental bridge patterns when compared with supplemental stuck-at patterns.

The scope and need for scan based transition tests in the context of high volume manufacturing testing of microprocessors is discussed. A classification of transition faults for latch based design is presented. Finally, we discuss a silicon experiment to understand the most fundamental issue of scan based transition testing viz. their robustness.

Traditionally, digital testing of integrated semiconductor circuits has focused on manufacturing defects. There is another class of failures that happens due to circuit marginalities. Circuit-marginality failures are on the rise due to shrinking process geometries, diminishing supply voltage, sharper signal-transition rates, and aggressive styles in circuit design. There are many different marginality issues that may render a circuit nonoperational. Capacitive cross coupling between interconnects is known to be a leading cause for marginality-related failures. In this paper, we present novel techniques to model and prioritize capacitive crosstalk faults. Experimental results are provided to show effectiveness of the proposed modeling technique on large industrial designs.

Power density of high-end microprocessors has been increasing by approximately 80% per technology generation, while the voltage is scaling by a factor of 0.8. This leads to 225% increase in current per unit area in successive generation of technologies. The cost of maintaining the same IR drop becomes too high. This leads to compromise in power delivery and power grid becomes a performance limiter. Traditional performance related test techniques with transition and path delay fault models focus on testing the logic but not the power delivery. In this paper we view power grid as performance limiter and develop a fault model to address the problem of vector generation for delay faults arising out of power delivery problems. A fault extraction methodology applied to a microprocessor design block is explained.

In this paper, we focus on the aspect of ground bounce due to the combination of current produced by gates (signals) switching and the flow of this current through pin electronics. We present a branch-and-bound test generation procedure to obtain high quality 2-vector tests that produce a large amount of ground bounce. We present a framework that accurately captures the relationship between a test and the associated relative size of the maximum amount of ground bounce while taking into account gate delay. Experimental results show that our search procedure can efficiently and effectively find a test that produces the maximum value of ground bounce. We also discuss a binary search based approach that allows our search to cover a larger portion of the search space and find a good test in a reduced amount of CPU time.

Due to technology scaling and increasing clock rate, problems due to noise effects lead to an increase in design and test efforts and a decrease in circuit performance. This paper addresses the problem of efficiently and effectively generating two vector tests to produce the maximum ground bounce in a circuit. We have developed a branch and bound procedure that can find a good quality test for maximum ground bounce in a rather short time. Comparison of results with SPICE simulations confirms the quality of tests obtained by our procedure.

Ground bounce in internal circuitry is becoming an important design validation and test issue. In this paper a new circuit model for ground bounce in internal circuitry is proposed. Based on this model an algorithm for generating test patterns that maximize ground bounce in combinational logic is presented. Our algorithm is also applicable to other test problems such as delay testing in the presence of excessive ground bounce.

Ground bounce occurs in integrated circuits and can cause signal distortion and increase gate delay. This can result in improper circuit operation. In the past, the switching of input/output buffers was the primary cause of the ground bounce. In designs employing deep sub-micron technology high operating frequency, and short rise/fall times, ground bounce due to switching in internal circuitry becomes a potential problem. In this paper experiments based on realistic assumptions are performed to explore the properties of ground bounce. Experiments indicate that (1) ground bounce is generated in gates, irrespective of whether outputs switch from 0 to 1 or from 1 to 0, (2) ground bounce is reduced when the load capacitance increases, and (3) ground bounce decreases when the number of gates that switch is held constant while the number of gates that don't switch increases. These conclusions are different from what has been found when input/output buffers switch and lead to new design, verification and test issues.

A building-block design for VLSI-based array dividers with concurrent error detection by recomputing using partitioned architecture (REPA) is proposed. The basic concept is that the divide array can be divided into two identical parts and its operation can be completed by using one part through two iterative calculations. With two such parts, a concurrent error detection scheme based on a space redundancy approach can be designed, and error detection is achieved at each iteration. The design is better than previous designs in terms of area requirement, time penalty, error detection capability, and detection period. Advanced analysis with m partitions is included. The experimental results are attractive, especially for certain designs with application-specified tradeoffs between speed performance and area cost.>