Based on a simplified nonlinear lumped element model of the electrodynamic loudspeaker in either a closed or a vented cabinet, a new nonlinear controller is derived, simulated and implemented on a DSP. The Volterra series expansion, a well known functional expansion to model nonlinear systems, is used to estimate the nonlinear parameters from distortion measurements. The controller is directly based on the nonlinear differential equation, and is tested for the case of a low frequency electrodynamic loudspeaker in a closed cabinet. Digital implementation is realized on a general purpose TMS320C30 DSP development board, using the automatic code generation from schematic entry of the Alta-Group SPW software.

In this paper a novel algorithm is presented for the efficient two-dimensional (2-D) symmetric noncausal finite impulse response (FIR) filtering and autoregressive (AR) modeling. Symmetric filter masks of general boundaries are allowed. The proposed algorithm offers the greatest maneuverability in the 2-D index space in a computational efficient way. This flexibility can be taken into advantage if the shape of the 2-D mask is not a priori known and has to be dynamically configured.>

In this paper a fast spatial adaptive algorithm is presented for the efficient least squares (LS), autoregressive exogenous (ARX), two-dimensional (2-D) modeling. Filter masks of general boundaries are allowed. Efficient space updating recursions are developed by exploiting the spatial shift invariance property of the 2-D data set.>

In this paper we will present an algorithm that is capable of recognizing symmetry in an electronic network graph in better than O((n+b)/sup 2/) time for typical circuits. Applications in symbolic analysis and behavioural modeling are presented.>

This paper presents a methodology to incorporate hierarchy in the design verification process of large full custom digital CMOS circuits including the effects of statistical process variation and variation in external parameters like temperature and supply voltage. Behavioural models are used to describe sub-circuits on a high level of abstraction. Statistical tolerance information from the circuit level is mapped onto the behavioural models. By means of a case study on a large full custom design we show that this design verification methodology can be very efficient.>

Generation of realistic images while supporting faster interaction is a topic in computer graphics research which has drawn considerable attention. Conventional frame buffer has been identified as a major bottle-neck for faster interaction [11]. Systolic Array Graphics (SAG) engines have been proposed to meet the above requirements by replacing the conventional frame buffer by a processor array. The speed limitations of the hardware restrict the use of SAG engines to displays resolutions of order 512x512 pixels when they are refreshed at 50Hz frame rate. In this paper we present an architectural solution to reduce the speed limitations of hardware. In the new architecture, a faster video stream is achieved by decoupling the speeds of the video and instruction streams by a multi-rate clocking scheme. We relax some timing constrains of the faster video stream by space domain multiplexing, i.e. using more wires.

CRACKER is an algorithm able to handle a large class of routing problems. Operating on a grid and using two wiring layers, it can deal with floating and fixed terminals, arbitrarily located in the routing area, and with obstacles in either of the two layers. The routing process consists of two stages. In the first stage, all nets are interconnected quickly, without avoiding conflicts with previously routed nets or obstacles. In the iterative second stage, connectivity-preserving local transformations are applied in a systematic way, such that, eventually, a solution without conflict is reached. There is no rip-up and reroute. The same algorithm is able to solve well-known examples of switchbox routing, routing with irregular boundaries, L-shaped channels, three-sided channels, etc.>

An algorithm for switchbox routing called PACKER is presented. In an initial phase, the connectivity of each net is established in a fast way without taking the other nets into account. In general, this gives rise to conflicts (short circuits). In the second stage the conflicts are removed iteratively using connectivity-preserving local transformations. They reshape a net by displacing one of its segments without disconnecting it from the net. The transformations are applied in a systematic way using a scan-line technique. During this process, a subset of the segments at the position of the scan line is densely packed in the (two) layers available for routing. The remaining segments are pushed to the next scan-line position. Scanning in the four available directions (left to right, right to left, top to bottom, and bottom to top) is performed until all conflicts have disappeared or no solution is found within a maximum number of iterations. It turns out that the new approach to routing, as implemented in PACKER, also has practical merits: most of the well-known benchmark examples are solved.>