This paper presents a dual-source energy harvesting interface for battery-free IoT devices, utilizing a serial-stacked single-inductor triple-input triple-output (SS-SITITO) buck-boost converter topology. In each charging cycle, the converter allows simultaneous power extraction from two energy harvesting sources and the usage of recycled energy in a storage capacitor. A two-dimensional maximum power point tracking (2D-MPPT) with triple-modulation realizes 98.3% accuracy in tracking the maximum power point for each input with minimal power cost. To provide sufficient output power under limited inputs, the system features energy recycling by automatically switching between sleep and active modes, and introduces a quad-phase buck-boost operation scheme, achieving up to 26mW maximum output power. To ensure self-sustainability with low quiescent power and enhanced power conversion efficiency, the circuit incorporates an edge-triggered feedback path, a power-optimized undervoltage lockout circuit, a low-voltage-supportable bandgap reference generator, and an ultra-low-power relaxation oscillator. Experimental results show a quiescent power consumption of 805nW, a 7000x power range, and a peak efficiency of 85.5%.

This paper proposes a reconfigurable wireless power receiver for NFC-powered battery-less electronic shelf label (ESL). It achieves both 13.56-MHz AC-DC regulating rectification and 1-MHz DC-DC buck-boost conversion by sharing the receiver coil and power stages. Considering that wireless power may not always be sufficiently available, the rectifier employs a storage capacitor to ensure charging stability under conditions of low input received power. Additionally, a bi-directional buck-boost converter (BD-BBC) has been proposed to achieve dual-output by sharing a core with a rectifier. It also enables the regulation of output voltage across a broad range of input voltages, thereby enhancing system design flexibility. For the storage capacitor serving as the input source for the BD-BBC, its utilization can also be improved. The chip is fabricated using a 0.18-$\mu $m CMOS process. The measurement results demonstrate a peak AC-DC rectification efficiency of 92.3% and a peak DC-DC conversion efficiency of 80.2% across a wide input voltage range.

This paper presents a 6.78-MHz wireless power and bidirectional data transfer system, which is intended for applications involving battery-less implantable gastric electrical stimulation (GES). The 0X/1X regulating rectifier achieves output voltage regulation without an additional DC-DC converter, thus enhancing power conversion efficiency (PCE) within the$R_{X}$. By utilizing transmission power regulation (TPR),$T_{X}$can adaptively adjust the transmission power according to the loading of the$R_{X}$, reducing the power consumption during sleep mode. Moreover, this paper proposes an innovative delay-shift keying (DSK) technique for forward data transmission, enabling simultaneous voltage regulation and achieving a power conversion efficiency (PCE) of 86.1% during data transmission. Both the$T_{X}$and the$R_{X}$chips were fabricated in a 0.18-$\mu $m BCD process, incorporating both 5-V and 12-V devices. During sleep mode, the consumption of the$T_{X}$is measured at 9.24 mW, which is a 64.3% reduction compared to the same system without PA deactivation. The rectifier and charge pump achieve peak efficiencies of 86.7% and 85.8%, respectively, at a stimulus current of 6mA.

This paper introduces a 6.78-MHz wireless power transfer (WPT) system for implantable medical devices (IMDs). The proposed dual-output resonant current-mode (RCM) rectifier cumulates energy from loosely-coupled coils and generates two output voltages (VH = 3-V, VL = 1.8-V) regulated by adaptive power control (APC) and local-loop power control. Due to transmission power regulation (TPR), the transmitter ($T_{X}$) delivers appropriate power to the receiver ($R_{X}$) to realize global-loop power control. Thus, the power transfer efficiency (PTE) is improved, especially under light load. Furthermore, zero-voltage switching and zero-current switching techniques enhance${R} _{X}$power conversion efficiency (PCE).$T_{X}$and$R_{X}$chips were fabricated in a 0.18-$\mu \text{m}$CMOS process. The measurement results show that the proposed WPT system successfully regulates outputs at VH = 3-V and VL = 1.8-V at a 1.5-cm coupling distance. With the proposed TPR, PTE is improved by 28.2% at PTOTAL = 1.6-mW, and input power is reduced by 94.8% at PTOTAL = 1-mW. The measured peak PCE and peak PTE are 85.1% and 31.3% at a coil distance of 10-mm, respectively.

This paper presents a single-inductor triple-output (SITO) buck-boost converter for wearable devices. It converts a 2.8V to 4.8V Li-ion battery voltage to three regulated output voltages: 1.2 V, 1.8V, and 3.3V for different back-end circuits, such as digital circuits and analog circuits. The converter operates at discontinuous conduction mode (DCM) and regulates the output using pulse-skip modulation (PSM) to reduce cross-regulation. Furthermore, the converter includes an adaptive on-time (AOT) generator to improve the output power range at low input voltage and control the maximum output voltage ripple under different inputs. Furthermore, three self-tracking zero current detectors (ST-ZCD) provide appropriate off-time periods for power MOSFETs to reduce the reverse inductor current. The measurement results show that the proposed SITO buck-boost converter achieves a maximum peak power conversion efficiency of 75.8% under 315mW output power. In addition, the peak inductor current is well controlled under different input voltages.

This paper presents a low-input-voltage (100 mV), low-output-voltage (500-600 mV) thermoelectric energy harvesting interface circuit for near-threshold energy-efficient Internet-of-Things (IoT) devices. The capacitive bootstrapping technique is used to generate a positive and negative bias pair for alleviating the significant conduction losses of power MOSFETs in a near-threshold operation. Internal bias voltages are automatically boosted to different levels as per the loading conditions to extend the output power range. The deployment of constant on-time digital pulse skip modulation with digital zero current detection (ZCD) achieves an ultralight load operation, and precluding a reverse current. The digital ZCD is capable of dynamically adjusting the off-time (TOFF) of the power transistors, which vary according to the input and output voltage levels. The proposed step-up dc-dc power converter implemented using a 180 nm CMOS technology demonstrates a maximum conversion efficiency of 76.4% over a 1 μW-500 μW load range, significantly evaluating the feasibility of the near-threshold interface circuit architecture for energy-efficient IoT devices.

This paper proposes a dual-mode digital buck converter with an automatic mode-select feature in a 0.18-μm CMOS for self-powered Internet-of-Things applications. The proposed converter combines the digital pulsewidth modulation and the proposed predetermined pulse-frequency modulation (PPFM) techniques to achieve both a high conversion efficiency and a wide output power range. The proposed PPFM technique calculates the appropriate OFF time of the power transistor in advance, eliminating the additional power budget requirement of the conventional zero-crossing detection circuit. From the results, it can be seen that the conversion efficiency improves by 21% under ultralight-load conditions. The available input voltage (VIN) ranges from 0.55 to 1.8 V for a wide variety of energy harvesters, and the output voltage (VOUT) ranges from 0.3 to 0.55 V to power the energy-efficient CMOS digital circuits. The proposed dual-mode digital buck converter achieves a maximum conversion efficiency of 90.5%, with an output power ranging from 25 nW to 10 mW. Owing to the proposed PPFM technique, the converter achieves a power conversion efficiency of more than 80%, with an output power of 200 nW to 10 mW.

IEEE 802.15.4e network aims at providing highly reliable communication links via time slotted channel hopping (TSCH) technology for lossy wireless channels. In such network, all nodes remain synchronized via message exchange periodically to compensate for the clock drift. In this paper, we derive theoretical average time for a node to remain in synchronized status with its parent node under the noisy channel scenario. Carried-out simulation results verify the correctness of our derived theoretical results.

Flash storage has been a standard component in Android devices. Recent research has reported that application data management in Android involves frequent fsync() operations. The current fsync() implementations, including those of ext4 and F2FS, have several common drawbacks. Specifically, ext4 commits a transaction every time to sync a file, whereas F2FS commits a checkpoint to sync a directory. Committing a transaction or checkpoint flushes all dirty data from the page cache to the flash storage via many small, random block write requests. The resultant high I/O frequency and excessive write traffic cause a high fsync() latency. This study presents an efficient fsync() method, called eager synching, which is based on a simple idea: write less, and write sequentially. To sync a file, eager synching writes only a subset of all dirty data in the page cache to a sequential log space using a few sequential block write requests. It does not involve transaction or checkpoint committing. We successfully implemented eager synching in ext4 and F2FS, and our experimental results show that, compared with the original fsync() methods of ext4 and F2FS, eager synching reduced the average and maximum fsync() latencies by up to 72% and 91%, respectively, block-level write traffic by up to 35%, and I/O frequency by up to 66%. Through enhanced crash recovery procedures, eager synching can successfully recover all previously synched files while still guaranteeing the file system integrity. We also conducted live application replays using the proposed eager synching approach and observed that this approach significantly improved the application frame updating rate and application execution time.

In this brief, we present a digital pulsewidth modulation buck converter with a switching loss reduction scheme to improve conversion efficiency at light load conditions. The proposed switching loss reduction scheme combines power-stage voltage swing scaling, transistor width scaling, and controller voltage scaling to reduce the dynamic power dissipation of the system. The power-stage voltage swing scaling also reduces the inductor current ripple at light load conditions, which extends the available output current range in the continuous conduction mode (CCM). A duty ratio estimation mechanism is implemented to provide a modulated signal with the correct duty ratio to control the output voltage. Experimental results demonstrate a 38% conversion efficiency improvement at a 50-μA output current. In addition, the proposed circuit achieves a 96% peak efficiency with an output current ranging from 20 μA to 30 mA in the CCM operation.

A 1V~1.2V battery input, 0.4V~0.6V output low-power all-digital power management unit (PMU) composed of a high-efficiency digital buck converter (DBC) and a fast-transient digital low drop-out (DLDO) regulator is developed for energy-efficient SoC applications. A fully integrated 2-to-1 switched-capacitor dc-dc converter is combined together to reduce the quiescent current of digital control circuits. The digital pulse width modulation (DPWM) with clock frequency gating further reduces the power consumption of buck converter in steady state. From experiment results, the peak power efficiency of the proposed buck converter is 90% with an output power range of 30μW to 3mW and the peak current efficiency of DLDO is 98.8% at 5mW. Moreover, the proposed DLDO achieves 92ns/130ns transition time in 60mV voltage step to dynamically scaling the voltage of supply voltage in digital circuits. This chip is designed and fabricated in 65nm CMOS process for verification.

A low voltage buck DC-DC converter (0.45-V input, 0.4-V output) with on-chip gate boosted (OGB) and clock frequency scaled digital PWM controller is designed in 40-nm CMOS process. The highest efficiency to date is achieved at the output power less than 40μW. In order to compensate for the die-to-die delay variations of a delay line in the proposed digital PWM controller, a linear delay trimming by a logarithmic stress voltage (LSV) scheme with good controllability is also proposed and verified in measurement.

In this paper, a fully integrated low voltage charge pump for thermoelectric energy harvesters is presented. The proposed dual-mode architecture achieves both the low startup voltage in a startup mode and high conversion efficiency in a normal operation mode without off-chip inductors and capacitors. In the measurement, the proposed circuit successfully converts 120-mV input to 770-mV output with 38.8% conversion efficiency.