The Internet of Vehicles and information security are key components of a smart city. Real‐time road perception is one of the most difficult tasks. Traditional detection methods require manual adjustment of parameters, which is difficult, and is susceptible to interference from object occlusion, light changes, and road wear. Designing a robust road perception algorithm is still challenging. On this basis, we combine artificial intelligence algorithms and the 5G‐V2X framework to propose a real‐time road perception method. First, an improved model based on Mask R‐CNN is implemented to improve the accuracy of detecting lane line features. Then, the linear and polynomial fitting methods of feature points in different fields of view are combined. Finally, the optimal parameter equation of the lane line can be obtained. We tested our method in complex road scenes. Experimental results show that, combined with 5G‐V2X, this method ultimately has a faster processing speed and can sense road conditions robustly under various complex actual conditions.

Bluetooth Low Energy (BLE) mesh which is the latest and the most innovative network technology has deeply changed the connection mode among massive BLE devices in Internet of Things (IoT). The study on the architecture and networking is quite necessary for the development of BLE Mesh. In IoT, the BLE devices are often used for voice, audio and data services. To satisfy the demands of diverse services and the mobility of the nodes, a hierarchical BLE mesh network (HBMN) architecture is proposed consisting of Hub Layer, Mesh Layer and User Layer. The HBMN architecture combines the star-network and mesh topology. Besides, the networking process of HBMN from the unprovisioned devices is also investigated in this paper. Moreover, two important performance measures have been analyzed and derived including networking time and single-hop delay. Finally, the access delay of one node is measured on the nRF52832 hardware platform. In addition, the networking time and single-hop delay of HBMN are evaluated and compared with the traditional BLE scatternet. The results show that the average single-hop delay of the BLE scatternet is 1.74 times as long as HBMN averagely and HBMN has a superior performance on the networking time when the network has a large number of devices.

In Mobile Ad hoc Networks (MANETs), the mobility of nodes causes frequent changes in the network topology, which directly affects user's Quality of Service (QoS) performance. Therefore, it is crucial for network operator to implement efficient routing optimization (RO) algorithms for diverse traffic flows. Based on the characteristics of centralized control routing in Software-Defined Networking (SDN), in this paper, we propose a routing optimization problem, and formulate the problem as an integer linear programming (ILP) problem. Then to solve the problem efficiently, we propose the QoS-aware routing optimization algorithm (QoS_ROA), which solves the problem in two stages. In the first stage, we use the Wavelet neural network (WNN) to predict the link quality at the next moment. In the second stage, we transform the proposed routing optimization problem into a 0–1 knapsack problem, and use differential search (DS) to solve it. The simulation results verify that, compared with the traditional routing algorithms, our algorithm can achieve high throughput, low packet drop rate, low delay in SDN-based MANETs.

DS (Decoupled-Superscalar) is a new microarchitecture that combines decoupled and superscalar techniques to exploit instruction level parallelism. Issue bandwidth is increased while circuit complexity growth is controlled with little negative impact on performance. Programs for DS are compiled into two instruction substreams: the dominant substream navigates the control flow and the rest of computational task is shared between the dominant and subsidiary substreams. Each substream is processed by a separate superscalar core realizable with current VLSI technology. DS machines are binary compatible with superscalar machines having the same instruction set, and a family of DS machines is binary compatible without recompilation. DS run time behavior is examined with an analytical model. A novel technique for controlling slip between substreams is introduced. Code partitioning issues of instruction count balancing and residence time balancing, important to any split-stream scheme, are discussed. Simulation shows DS achieves performance comparable to an aggressive superscalar, but with potentially less complex hardware and faster clock rate.