Recent studies have demonstrated that Vision Transformers (ViTs) are vulnerable to adversarial attacks. While adversarial training is a recognized strategy for enhancing model robustness, it demands substantial computational resources during the training process. Furthermore, the high computational complexity of ViTs during inference presents further challenges. To address these challenges, we propose token pruning-based adversarial tuning for robust ViTs (PAT-ViT). PAT-ViT enhances the robustness of ViTs by reducing their predictability to attackers and tuning them using adversarial data. Unlike conventional methods, PAT-ViT reduces training overhead by tuning pre-trained ViTs rather than training ViTs from scratch. Moreover, PAT-ViT improves inference efficiency by pruning partial input image. Compared to the state-of-the-art (SOTA) robust method, PAT-ViT boosts robust accuracy by 7.5% while also achieving a 10.3% increase in clean accuracy. During inference, PAT-ViT reduces FLOPs by 0.7× relative to SOTA. Additionally, it reduces the training time by 7.5× to 13.1× compared to prior works.

To overcome the von Neumann bottleneck, computing-in-memories (CIMs) have emerged as a design trend. On the other hand, with the globalization of the semiconductor supply chain, hardware Trojans have become a significant security concern. While there have been some studies on hardware Trojan designs for embedded memories in the past, there is no literature addressing hardware Trojan designs for CIMs. In this article, we propose a hardware Trojan design for spin transfer torque magnetoresistive random access memory (STT-MRAM)-based CIMs that can disrupt computing-mode operations. Our trigger circuit can evade detection during post-manufacturing memory testing, and our payload circuit can disrupt over 99% of CIM operations. Experimental results also demonstrate that compared to the original peripheral circuits of STT-MRAM-based CIMs, the area overhead and power overhead (at the TT process corner) caused by our inserted hardware Trojan are only 1.023% and 0.123%, respectively. Therefore, our hardware Trojan can easily hide within the peripheral circuits.

Utilizing gate camouflaging-based obfuscation is an effective method to protect ICs against reverse engineering attacks. Nonetheless, because camouflaged logic gates exhibit greater delays than standard logic gates, integrating camouflaged logic gates may potentially introduce timing violations. To ensure timing closure, this paper introduces a timing-driven design flow for incorporating camouflaged logic gates. For camouflaged logic gates that have been integrated into the gate-level netlist, we perform timing-driven placement to meet timing constraints. Additionally, we also insert camouflaged gates as spare cells for metal-only ECO. We have developed both a security-driven ECO algorithm and a timing ECO algorithm to maximize security under timing constraints by fully utilizing the timing slacks on non-critical paths. Experiment data show that, compared to previous design methodologies, the proposed approach can optimize security and achieve timing closure simultaneously.

Spin-transfer-torque magnetic random access memory (STT-MRAM) has been considered as a candidate for next-generation memory to cope with the scaling challenges of conventional memories. However, the STT-MRAM has the problem of high read failure rate. Effective reliability-enhancement techniques thus are needed for STT-MRAMs. In this paper, we propose a fault-aware error-correction-code (FA-ECC) scheme for STT-MRAMs. The FA-ECC scheme can distinguish a read disturb fault (RDF) from an incorrect read fault (IRF) such that the IRF can be recovered by adjusting the reference resistance to avoid the effect of fault accumulation. Thus, the FA-ECC scheme can be used for concurrent error detection and correction or scrubbing. Analysis results show that the area cost of the FA-ECC scheme is only about 1711μm2using TSMC 40nm CMOS technology for a STT-MRAM with 64-bit words. Also, the FA-ECC scheme can significantly improve the reliability of STT-MRAM in comparison with a conventional ECC scheme.

A reconfigurable wrapper provides the flexibility for a core test to utilize different bandwidths of test access mechanism (TAM) at different test time points. By using reconfigurable wrappers, the lower bound of total test application time can be achieved. However, since reconfigurable wrappers attempt to utilize TAM bandwidth as fully as possible, they often consume a lot of routing resources. In advanced technology nodes, routability has become a critical and difficult issue. In this paper, based on reconfigurable wrappers, we present the first work that studies the correlation between grid-based TAM wire routing and test scheduling. Our objective is to derive a feasible grid-based TAM wire routing solution with the minimum total test application time. Compared with previous works, the main advantage of our approach is that it can resolve the grid-based TAM wire routing congestion problem during test scheduling. Benchmark data show that our approach can effectively and efficiently minimize the total test application time under grid-based routing congestion constraints.

Built-in-self-test (BIST) is a useful technique for memory testing, but the synthesis of memory BIST controllers for 3D ICs (three-dimensional ICs) has not been well studied. In this paper, we propose a two-stage approach to synthesize the memory BIST controllers of a 3D IC under power constraints: the first stage performs memory grouping and the second stage performs test scheduling (including both pre-bond testing and post-bond testing). Compared with the previous work, our approach has the following two advantages: (1) our approach allows a memory BIST controller to perform parallel memory tests; (2) our approach allows a memory test to start from any time point within a session. Thus, our approach has a higher flexibility for both memory grouping and test scheduling. Benchmark data consistently show that our approach can reduce both the test application time and the circuit area overhead at the same time.

The CAD Contest at ICCAD[1], [2], [3], [4], [5], [6] is a challenging, multi-month R&D competition, focusing on modern and practical problems at the forefront of Electronic Design Automation (EDA). In its sixth year, the 2017 CAD Contest at ICCAD is among the premier worldwide academic programming contests, attracting 122 teams from 10 different regions/countries. This year, three contest problems in the areas of ECO logic synthesis, ECO routing and placement legalization for the advanced nodes are called for competition. We hope that the contest evaluation frameworks and benchmarks boost research on these critical problems and help EDA community discover novel, efficient, high-quality solutions to advance the state-of-the-art in EDA.

In advanced technologies, on-chip-variation (OCV) has accounted for a large proportion of clock skew, which limits the performance of a circuit. To mitigate the OCV problem, a mesh structure has been widely used in high-performance designs. Unfortunately, clock mesh structure also causes large power consumption and large power-ground surge current. Therefore, recently, several approaches have been proposed to apply resonant clock to reduce power consumption. However, previous works often suffer from area overhead because of the need to insert large decoupling capacitors. In this paper, we propose a novel resonant clock mesh structure, called ping-pong mesh, to overcome these drawbacks. Our ping-pong mesh contains two submeshes, each of which plays the role of the decoupling capacitor of the other, and the clocks in two submeshes operate in completely opposite phases. Our ping-pong mesh has the following two advantages: 1) a ping-pong mesh does not need additional decoupling capacitors as in previous works and 2) a ping-pong mesh can reduce the power-ground surge current about half of previous works. Benchmark data consistently show that our ping-pong mesh does work well in practice.

The CAD Contest at ICCAD is a challenging, multi-month competition, focusing on advanced, real-world problems in the field of Electronic Design Automation (EDA). In its fifth year, the 2016 CAD Contest at ICCAD attracted 135 teams from 11 regions/countries. Three critical EDA problems, in the areas of design verification, logic synthesis, and design for manufacturing (DFM), were called for competition this year. We hope that the contest benchmark suites and evaluation infrastructure boost research in the related areas and help EDA community find novel and high-quality solutions to the problems.

Clock gating is recognized as one of the most effective techniques to reduce the dynamic power consumption. Many research efforts have been paid to build activity-driven clock trees for low power designs. On the other hand, as the feature size continues to shrink, the on-chip-variation (OCV) effect has become a serious concern, especially for the clock skew of the top-level clock tree. Based on this observation, in this paper, we present the first work for the synthesis of OCV-aware top-level activity-driven clock trees. In our approach, the clock skew variation is considered during the top-level activity-driven clock tree synthesis. Our objective is to minimize the weighted sum of the worst timing slack and the power consumption. Compared with previous works, benchmark data consistently show that our approach can greatly increase the worst timing slack with a small overhead on the power consumption.

In a multipower-mode design, as the range of the supply voltage becomes wide, a large clock skew may occur among different power domains. To remove this clock skew, conventional power-mode-aware buffers (PMABs) require a large overhead on power consumption. In this brief, we propose a new PMAB architecture for wide-voltage-range multipower-mode designs. The proposed PMAB architecture is composed of two serially connected sub-PMABs at two different voltage levels, respectively. In the front sub-PMAB, the low voltage level is used for coarse-grained clock skew minimization. In the back sub-PMAB, the high voltage level is used for fine-grained clock skew minimization. Benchmark data show that the proposed approach can effectively eliminate the clock skew with small power consumption.

The 2015 CAD Contest at ICCAD presents cutting-edge, real-world EDA problems and challenging benchmarks derived from modern industrial designs. It also provides a standard, publicly available evaluation framework for each of the problems. The ever-increasing complexity of integrated circuit design has brought forth new and challenging problems for the EDA community. These require novel, efficient, and high-quality algorithms and methodologies. It is our hope that the CAD Contest at ICCAD would encourage timely and much-needed research on these critical problems in the field of EDA.

In the design of nonzero clock skew circuits, an increase of the short-path delay may improve circuit speed or reduce leakage power. However, the impact of increasing the short-path delay on the trade-off between circuit speed and leakage power has not been well studied. An analysis of previous works shows that they can be classified into two independent groups. One group uses extra buffers to increase the short-path delay for achieving the lower bound of the clock period; however, this group has a large overhead of leakage power. The other group uses the combination of threshold voltage assignment and gate sizing (TVA/GS) to increase the short-path delay as possible for reducing leakage power; however, this group often does not work with the lower bound of the clock period. Accordingly, this article considers the simultaneous application of buffer insertion and TVA/GS during clock skew scheduling. Our objective is to minimize the leakage power for working with the lower bound of the clock period. To the best of our knowledge, our approach is the first leakage-power-aware clock skew scheduling that guarantees working with the lower bound of the clock period. Benchmark data consistently show that our approach achieves good results in terms of both the circuit speed and the leakage power.

In the design of nonzero clock skew circuits, an increase of the path delay may improve circuit speed and reduce leakage power. However, the impact of increasing path delay on the trade-off between circuit speed and leakage power has not been well studied. In this paper, we propose a two-step approach for leakage-power-aware clock period minimization. Compared with previous works, our approach has the following two significant contributions. First, our approach is the first leakage-power-aware clock skew scheduling that can guarantee working with the lower bound of the clock period. Second, our approach is also the first work that demonstrates the problem of minimizing the number of extra buffers is a polynomial-time problem. Benchmark data show that our approach achieves the best results in terms of the clock period and the leakage power.

Although intentional clock skew can be utilized to reduce the clock period, its application in gated clock designs has not been well studied. A gated clock design includes both data paths and clock control paths, but conventional clock skew scheduling only focus on data paths. Based on that observation, in this paper, we propose an approach to perform the co-synthesis of data paths and clock control paths in a nonzero skew gated clock design. Our objective is to minimize the required inserted delay for working with the lower bound of the clock period (under clocking constraints of both data paths and clock control paths). Different from previous works, our approach can guarantee no clocking constraint violation in the presence of clock gating. Experimental results show our approach can effectively enhance the circuit speed with almost no penalty on the power consumption.

As the supply voltage is down to the ultra-low voltage (ULV) level, timing closure becomes a serious challenge in the use of multiple power modes. Due to a wide voltage range, a very huge clock skew may occur among different power modes. To reduce this huge clock skew, the conventional power-mode-aware clock tree often suffers from a huge overhead on power consumption. Moreover, at the ULV level, since the setup time and the hold time of each register dramatically increase, the number of timing violations also increases greatly. However, the existing minimum padding technique cannot fix hold time violations in multiple power modes. Based on those two observations, in this paper, we propose a low-power timing closure methodology, which incorporates the synthesis of clock tree and data path, for multipower-mode ULV designs. Our low-power timing closure methodology has two main approaches. First, we use multiple power modes to build a power-mode-aware clock tree for reducing clock skew with very small power consumption. Second, we propose the first multi-power-mode minimum padding technique to fix all the hold time violations in all the power modes simultaneously. Experimental results consistently show that the integration of both approaches yields the best results.

In advanced CMOS technology, the NBTI (negative bias temperature instability) effect results in delay degradations of PMOS transistors. Further, because of clock gating, PMOS transistors in a clock tree often have different active probabilities, leading to different delay degradations. If the degradation difference is not properly controlled, this clock skew may cause the circuit fails to function at some point later in time. Intuitively, the degradation difference can be eliminated, if we increase the active probability of the low-probability clock gates to ensure the clock gates at the same level always having the same active probability. However, this intuitive method may suffer from large power consumption overhead. In this article, we point out, by carefully planning the transistor-level clock signal propagation path, we can have many clock gates whose active probabilities do not affect the degradation difference. Based on that observation, we propose a critical-PMOS-aware clock tree design methodology to eliminate the degradation difference with minimum power consumption overhead. Benchmark data consistently show our approach achieves very good results in terms of both the NBTI-induced clock skew (i.e., the degradation difference) and the power consumption overhead.

Although clock skew can be utilized to reduce the clock period, the utilization of clock skew also limits the sharing of resources (including registers and functional units). Previous works have considered the influence of clock arrival times on register sharing, but they do not pay any attention to the influence of clock arrival times on functional unit sharing. As a result, extra functional units are often required during functional unit binding. Based on that observation, in this paper, we perform the simultaneous application of register binding and functional unit binding for the high-level synthesis of nonzero clock skew circuits. Our objective is to minimize the circuit area for working with the lower bound of the clock period. Compared with previous works, benchmark data show that our approach can achieve the lower bound of the clock period with a smaller area overhead.

Dual threshold voltage (dual-Vth) assignment is recognized as a useful technique to reduce the leakage power. However, as the process technology shrinks to the deep sub-micron regime, the negative bias temperature instability (NBTI) effect becomes a serious concern. The NBTI effect may cause the degradation of threshold voltage over a period of months or years. Since previous dual-Vth assignment techniques do not consider the NBTI effect, they often decrease the circuit lifetime. In this paper, we propose an NBTI-aware dual-Vth assignment algorithm. Our objective is not only to reduce the leakage power but also to maintain the lifetime of the circuit. By assigning independent candidate gates to high threshold voltage (HTV) simultaneously, in each benchmark circuit, our approach can achieve a better result with a smaller CPU time. Experimental data consistently show that our approach works well in practice.

With the advent of deep sub micron era, design closure is becoming harder to achieve. In high-level synthesis, slack is a very effective means of tolerating uncertainties. Thus, several research efforts have been paid to study the slack-driven high-level synthesis problem. However, previous works cannot actually maximize the total slack value, because they are limited to either the operation scheduling stage or the resource binding stage. In this paper, we study the simultaneous operation scheduling and resource binding for the maximization of the total slack value. An integer linear programming approach is proposed for formally draw up the slack-driven high-level synthesis problem. Note that our approach guarantees maximizing the total slack value. Compared with the combination of previous works (i.e., slack-driven operation scheduling followed by slack-driven resource binding), experimental data show that our approach can greatly reduce the total slack value without any design overhead.

Due to clock gating, the PMOS transistors in the clock tree often have different active probabilities, which lead to different NBTI delay degradations. To ensure that the clock skew is always zero, there is a demand to eliminate the degradation difference. In this paper, we present a critical-PMOS-aware clock tree design methodology to deal with this problem. First, we prove that, under the same tree topology, the NAND-type-matching clock tree has the minimum number of critical PMOS transistors. Then, we propose a 0–1 ILP (integer linear programming) approach to minimize the power consumption overhead while eliminating the degradation difference. Benchmark data consistently show that our design methodology can achieve very good results in terms of both the clock skew (due to the degradation difference) and the power consumption overhead.

The power gating technique is useful in reducing standby leakage current, but it increases the gate delay. For a functional unit, its maximum allowable delay (for a target clock period) limits the smallest standby leakage current its power gating can achieve. In this paper, we point out: in the high-level synthesis of a non-zero clock skew circuit, the resource binding (including functional units and registers) has a large impact on the maximum allowable delays of functional units; as a result, different resource binding solutions have different standby leakage currents. Based on that observation, we present the first work to draw up the timing driven power gating in high-level synthesis. Given a target clock period and design constraints, our goal is to derive the minimum-standby-leakage-current resource binding solution. Benchmark data show: compared with the existing design flow, our approach can greatly reduce the standby leakage current without any overhead.

Power gating is the most effective technique to reduce the leakage power of an idle functional unit. However, when the functional unit is turned on, a sudden discharge, called surge current, is induced. If too many functional units are turned on simultaneously, the instantaneous accumulated surge current may lead to the malfunction of the circuit. In this paper, we point out the high-level synthesis (including operation scheduling and functional unit binding) has a great impact on the maximum surge current. Then, based on that observation, we propose an integer linear program (ILP) to formally draw up the surge current minimization problem in the high-level synthesis stage. Compared with the existing design flow, benchmark data show that our approach can significantly reduce the maximum surge current without any design overhead.

This paper points out that register binding in the high-level synthesis stage has a significant impact on the clocking constraints between registers. As a result, different register binding solutions often lead to different smallest feasible clock periods. Based on that observation, we formally draw up the problem of register binding for clock-period minimization. Compared with the left edge algorithm, experimental data show that, in most benchmark circuits, our approach can greatly reduce the clock period without any overhead on the number of registers.

In a synchronous sequential circuit, huge current peaks are often observed at the moment of clock transition (since all registers are clocked). Previous works focus on reducing the number of switching registers. However, even though the switching registers are the same, different combinations of switching directions still result in different peak currents. Based on that observation, in this article, we propose an ECO (engineering change order) approach to minimize the peak current by considering the switching directions of registers. Our approach is well suitable for reducing the peak current in IC testing. Experimental data consistently show that our approach works well in practice.

Clock skew minimization is always very important in the clock tree synthesis. Due to clock gating, the clock tree may include different types of logic gates, e.g., AND gates, OR gates, and buffer gates. If the logic gates at the same level are in different types, which have different timing behaviors, the control of clock skew becomes difficult. Based on that observation, in this paper, we present a novel clock tree design style, called type-matching clock tree, to ensure that the logic gates at the same level are in the same type. We prove that any clock control logic can always be transformed to our type-matching clock tree. Then, based on the idea of type-matching clock tree, we propose a zero skew gated clock tree synthesis algorithm. Compared with the industry-strength gated clock tree synthesis, experimental data show that our approach can significantly reduce the clock skew in every process corner with a small penalty on the clock tree area and the clock tree power consumption.

The combination of clock skew scheduling and delay insertion may lead to further clock period reduction. Although some previous works can minimize the clock period, they only heuristically reduce the required inserted delay. However, since the delay insertion is an ECO (engineering change order) process, minimizing the required inserted delay is very important for the design closure, In this paper, we present a linear program to formally formulate the simultaneous application of clock skew scheduling and delay insertion. Our objective is not only to achieve the lower bound of the clock period, but also to achieve the lower bound of required inserted delay. Compared with previous works, our paper has the following two significant contributions: (1) our approach is the first work that guarantees solving this problem optimally; and (2) our paper is the first proof of showing that the time complexity of this problem is polynomial.

In this article, we provide a fresh viewpoint to the interactions between clock skew scheduling and delay insertion. A race-condition-aware (RCA) clock skew scheduling is proposed to determine the clock skew schedule by taking race conditions (i.e., hold violations) into account. Our objective is not only to optimize the clock period, but also to minimize heuristically the required inserted delay. Compared with previous work, our major contribution includes the following two aspects. First, our approach achieves exactly the same results, but has significant improvement in time complexity. Second, our viewpoint can be generalized to other sequential timing optimization techniques.

Given several specific clocking domains, the peak current minimization problem can be formulated as a 0-1 integer linear program. However, if the number of binary variables is large, the run time is unacceptable. In this paper, we study the reduction of this high computational expense. Our approach includes the following two aspects. First, we derive the ASAP schedule and the ALAP schedule to prune the redundancies without sacrificing the exactness (optimality) of the solution. Second, we propose a zone-based scheduling algorithm to solve a large circuit heuristic ally.

In modern high-speed circuit design, the clock skew has been widely utilized as a manageable resource to improve the circuit performance. However, in high-level synthesis stage, the circuit is never optimized for the utilization of clock skew. This paper is the first attempt to the high-level synthesis of non-zero clock skew circuits. First, we show that the register binding in high-level synthesis stage has a significant impact on the clocking constraints between registers. As a result, different register binding solutions lead to different smallest feasible clock periods. Then, based on that observation, we formulate the problem of register binding for clock period minimization. Given a constraint on the number of registers, our objective is to find a minimum-period register binding solution. Experimental data show that, in most benchmark circuits, the lower bound of the clock period can be achieved without any extra overhead on the number of registers.

In a synchronous finite state machine (FSM), huge current peaks are often observed at the moment of state transition. Previous low power state encoding algorithms focus on the reduction of switching activities of state registers (i.e., state bits). However, even though the switching state registers are the same, different combinations of switching directions still result in different peak currents. Based on that observation, in this paper, we propose the first approach to re-encode an FSM by considering the switching directions of state registers in order to minimize the peak current caused by the state transition. Experimental data consistently show that the peak current is reduced with no penalty.

It is well known that the clock skew can be exploited as a manageable resource to improve circuit performance. However, due to the limitation of race conditions, the optimal clock skew scheduling often does not achieve the lower bound of sequential timing optimization. This paper proposes a polynomial time complexity algorithm, called delay insertion and nonzero skew algorithm (DIANA), which considers delay insertion to determine the clock skew schedule. The objective here is not only to optimize the clock period but also to heuristically minimize the required inserted delay for resolving the race conditions. Experiments with benchmark circuits consistently demonstrate that the proposed approach achieves the lower bound of sequential timing optimization. Moreover, since the DIANA algorithm attempts to minimize the required inserted delay between two registers, the feasible value for delay insertion is within a very large range. Therefore, even though only the buffers in a standard cell library are used to implement the delay insertion, a feasible solution is easily found.

The race conditions often limit the smallest feasible clock period that the optimal clock skew scheduling can achieve. Therefore, the combination of clock skew scheduling and delay insertion (for resolving the race conditions) may lead to further clock period reduction. However, the interactions between clock skew scheduling and delay insertion have not been well studied. In this paper, we provide a fresh viewpoint to look at this problem. A novel approach, called race-condition-aware (RCA) clock skew scheduling, is proposed to determine the clock skew schedule by taking the race conditions into account. Our objective is not only to optimize the clock period, but also to heuristically minimize the required inserted delay. Compared with previous work, our approach has significant improvement in the time complexity.

Although a lot of research efforts have been made in the minimization of the total power consumption caused by the clock tree, no attention has been paid to the minimization of the peak current caused by the clock tree. In this paper, we propose an opposite-phase scheme for peak current reduction. Our basic idea is to divide the clock buffers at each level of the clock tree into two sets: an half of clock buffers operate at the same phase of the clock source, and another half of clock buffers operate at the opposite phase of the clock source. Consequently, our approach can reduce the peak current of the clock tree nearly 50%. Experimental data consistently show that our approach works well in practice.

We present a high-speed VLSI fuzzy logic controller, which is well suitable for real time applications. The main distinction of our approach is that it may complete the max-min calculation within one clock cycle. The speedup is achieved by an effective format for membership function and a careful analysis to the conditions of max-min calculation. As a result, the latency of a fuzzy inference can be considerably reduced. Based on the basic idea, a pipelined parallel architecture is proposed to fully utilize the parallelism inherited in the fuzzy inference. The VLSI fuzzy logic controller was implemented and simulated by using 0.35 /spl mu/m cell library as the target technology. Experimental data shows that the proposed architecture achieves higher performance compared with other approaches.

No abstract available.