We present the design and characterization of amplifiers and control logic for an integrated circuit designed to record electrocorticograms (ECoG) from the surface of the brain. The chip, which was fabricated in a 0.6-μm BiCMOS process, contains 100 amplifiers, control logic, and circuits for wireless power and transmission of data. ECoG signals, sensed by electrodes, are capacitively coupled to the amplifiers. Each amplifier has a gain of 59.2 dB, a maximum bandwidth of 240 Hz, an input referred noise of 2.8μV, and consumes 4.5μW of power. The output of each amplifier is connected to a 10-bit ADC via an adaptive-bias buffer and transmission gate whose transparency is set by the control logic. The control logic time-shares the ADC by multiplexing through one of five preset patterns of 32 on-chip signals. The digitized waveforms are then broadcasted wirelessly using a 900 MHz FSK transmitter. The entire chip consumes 7.2 mW of power during operation.

We have developed a miniature telemetry system that captures neural, EMG, and acceleration signals from a freely moving insect and transmits the data wirelessly to a remote digital receiver. The system is based on a custom low-power integrated circuit that amplifies and digitizes four biopotential signals as well as three acceleration signals from an off-chip MEMS accelerometer, and transmits this information over a wireless 920-MHz telemetry link. The unit weighs 0.79 g and runs for two hours on two small batteries. We have used this system to monitor neural and EMG signals in jumping and flying locusts.

We present experimental results from an integrated circuit designed for wireless neural recording applications. The chip, which was fabricated in a 0.6-mum 2P3M BiCMOS process, contains 100 amplifiers and a 10-bit ADC and 902-928 MHz FSK transmitter. Neural signals from one amplifier are sampled by the ADC at 15.7 kSps and telemetered over the FSK wireless data link. Power, clock, and command signals are sent to the chip wirelessly over a 2.765-MHz inductive (coil-to-coil) link. The chip is capable of operating with only two off-chip components: a power receive coil and a 100-nF capacitor.

The ability to monitor the simultaneous electrical activity of multiple neurons in the brain enables a wide range of scientific and clinical endeavors. Recent efforts to merge miniature multielectrode neural recording arrays with integrated electronics have revealed significant circuit design challenges. Weak neural signals must be amplified and filtered using low-noise circuits placed close to the electrodes themselves, but power dissipation must strictly be limited to prevent tissue damage due to local heating. In modern recording systems with 100 or more electrodes, raw data rates of 15 Mb/s or more are easily produced. Micropower wireless telemetry circuits cannot transmit information at such high rates, so data reduction must be performed in the implanted device. In this paper, we present integrated circuits and design techniques that address the twin problems of neural signal amplification and data reduction for this severely size- and power-limited application.

Due to limited battery life and size limitations, many implantable biomedical devices must be powered inductively. Because of weak coupling between implanted and external coils, obtaining high power efficiency is a challenge. Previous authors have addressed the issue of optimizing power efficiency in these systems. In this paper, we further this analysis for the case of planar spiral "pancake" coils at low RF frequencies (100 kHz -10 MHz). We consider practical design constraints such as component variation, power amplifier limitations, and coil voltage limits. We introduce a new, complete expression for total power link efficiency.

For many medical applications, neural recording systems should be fully implantable. Transcutaneous wires must be completely eliminated, and this necessitates the wireless transfer of power, clock, and configuration data to the device. We have developed, fabricated, and tested circuits that recover power from a wireless power transmitter and produce a clock from its carrier. A novel data recovery scheme is also presented that allows configuration and command data to be recovered from the amplitude-modulated power waveform. This scheme is robust against glitches and offsets, and requires a minimum modulation depth of 29%. All of these circuits together consume 0.366 mm2of area in a 0.5-mum CMOS process and have a total current draw of 511 muA

This paper presents a new random-search based integrated inductor optimization algorithm. The algorithm provides the designer with valuable information about design tradeoffs. It is used to design an inductor to minimize power dissipation in an LC VCO. The measured results show that a 53:1 power savings can be achieved over VCOs using inductors optimized only for maximum Q. Six 433-MHz VCOs were fabricated and measured. The VCO using the optimal inductor design has a measured minimum power dissipation of 1.2 mW in a 0.5-mum three-metal CMOS process

We are developing a fully-implantable neural recording system with wireless power and data transfer. As part of this system, we have developed a low-power integrated circuit that performs power rectification and regulation, reception of configuration data, neural signal amplification and filtering, spike detection, neural signal digitization and RF transmission. The chip includes 88 amplifiers having a gain of 60 dB from 1 to 5 kHz. An integrated ADC operates at 15 kSamples/sec with 9-bit resolution. A 433-MHz RF transmitter uses FSK modulation to transmit one digitized neural signal and spike detection data from all channels. Total power consumption is 13.5 mW

In recent years, computational biologists have shown through simulation that small neural networks with fixed connectivity are capable of producing multiple output rhythms in response to transient inputs. It is believed that such networks may play a key role in certain biological behaviors such as dynamic gait control. In this paper, we present a novel method for designing continuous-time recurrent neural networks (CTRNNs) that contain multiple embedded limit cycles, and we show that it is possible to switch the networks between these embedded limit cycles with simple transient inputs. We also describe the design and testing of a fully integrated four-neuron CTRNN chip that is used to implement the neural network pattern generators. We provide two example multipattern generators and show that the measured waveforms from the chip agree well with numerical simulations.

We have designed and tested a single-chip analog VLSI sensor that detects imminent collisions by measuring radially expansive optic flow. The design of the chip is based on a model proposed to explain leg-extension behavior in flies during landing approaches. A new elementary motion detector (EMD) circuit was developed to measure optic flow. This EMD circuit models the bandpass nature of large monopolar cells (LMCs) immediately postsynaptic to photoreceptors in the fly visual system. A 16 × 16 array of 2-D motion detectors was fabricated on a 2.24 mm × 2.24 mm die in a standard 0.5-µm CMOS process. The chip consumes 140 µW of power from a 5 V supply. With the addition of wide-angle optics, the sensor is able to detect collisions around 500 ms before impact in complex, real-world scenes.

A design approach is presented for soft-decision decoding of block product codes ("block turbo codes") using analog computation with MOS devices. Application of analog decoding to large code sizes is also considered with the introduction of serial analog interfaces and pipeline schedules.

Integrating sensorimotor systems is still a difficult problem for robotics. Biological inspiration, which has been effectively used to address single sensorimotor tasks, could also be applied to this problem. Several studies on the cricket suggest that it integrates an optomotor response to improve its sound localization behaviour. We have taken two existing 'biorobots'-one that uses an a VLSI circuit to reproduce the optomotor behaviour and another that models in hardware and software the sound localization of the cricket-and combined their capabilities to investigate whether an additive combination will reproduce these effects. We report the initial results and discuss a number of issues raised by this investigation.

The complexity of analog VLSI systems is often limited by the number of pins on a chip rather than by the die area. Currently, many analog parameters and biases are stored off chip. Moving parameter storage on chip could save pins and allow us to create complex programmable analog systems. In this paper, we present a design for an on-chip non-volatile analog memory cell that can be configured in addressable arrays and programmed easily. We use floating-gate MOS transistors to store charge, and we use the processes of tunneling and pFET hot-electron injection to program values. With these designs, we achieve greater than 13-bit output precision with a 39 dB power supply rejection ratio and no crosstalk between memory cells.

Flies are capable of stabilizing their body during free flight by using visual motion information to estimate self-rotation. We have built a hardware model of this optomotor control system in a standard CMOS VLSI process. The result is a small, low-power chip that receives input directly from the real world through on-board photoreceptors and generates motor commands in real time. The chip was tested under closed-loop conditions typically used for insect studies. The silicon system exhibited stable control sufficiently analogous to the biological system to allow for quantitative comparisons.

Flies are capable of rapid, coordinated flight through unstructured environments. This flight is guided by visual motion information that is extracted from photoreceptors in a robust manner. One feature of the fly's visual processing that adds to this robustness is the saturation of wide-field motion-sensitive neuron responses with increasing pattern size. This makes the cell's responses less dependent on the sparseness of the optical flow field while retaining motion information. By implementing a compartmental neuronal model in silicon, we add this "gain control" to an existing analog VLSI model of fly vision. This results in enhanced performance in a compact, low-power CMOS motion sensor. Our silicon system also demonstrates that modern, biophysically-detailed models of neural sensory processing systems can be instantiated in VLSI hardware.