With growing concerns over physical security against power and electromagnetic side-channel attacks (SCA), this work provides a comprehensive analysis of different existing isolation countermeasures, especially the analysis of security-focused shunt low-dropout regulators (LDOs). Using both small-signal and large-signal analysis, we demonstrate that shunt LDOs offer superior security using the metric current-domain signature attenuation (CDSA) and load supply isolation (LSI) performance while mitigating mid-frequency power-supply ripple-rejection (PSR) peaking. Various existing shunt LDO architectures are evaluated, highlighting trade-offs between DC rejection and high-frequency CDSA response. Alternative isolation techniques such as galvanic isolation, digital LDOs, and integrated voltage regulators (IVRs) are also examined.

Continuous remote monitoring of implantable medical devices, such as pacemakers, is limited by the high power consumption and security concerns of traditional wireless technologies like Bluetooth. In this work, we investigate Electro-Quasistatic Human Body Communication (EQS-HBC) as an alternative, leveraging the body itself as a communication channel between implants and wearable devices. EQS-HBC achieves real-time, high-throughput data transmission at power levels approximately 100 times lower than Bluetooth, enabling millisecond-resolution monitoring with minimal impact on device longevity. Through system-level optimization of sensing, memory, and communication, we demonstrate that EQS-HBC can support high temporal-resolution, secure data exchange without the high battery life penalties of current Radio-Frequency (RF) based solutions. These results highlight EQS-HBC's potential to transform remote care for patients by making truly continuous, personalized monitoring feasible.

Electroencephalography (EEG) is a widely used method for monitoring brain activity. Traditionally, wet electrodes have been the preferred choice due to their superior signal-to-noise ratio (SNR). However, as the demand for wearable and long-term EEG systems grows, researchers are increasingly exploring dry electrodes, which offer greater practicality despite their lower SNR. In this paper, we analyze how system parameters affect the noise characteristics that contribute to the lower SNR in dry EEG systems. Through experimental measurements and theoretical insights, we examine key factors influencing signal quality, particularly contact impedance and uncorrelated pickup. Specifically, we demonstrate that increasing pressure and electrode contact area significantly reduces noise levels, by approximately 50 dB and 30 dB, respectively, by lowering contact impedance. Furthermore, we observe that while dry electrodes maintain stable noise levels over time, wet electrodes experience a significant noise increase of approximately 38 dB after just two hours. Additionally, we highlight the presence of flicker noise in dry EEG systems, a phenomenon previously overlooked in this context. Our findings provide critical insights into the noise behavior of dry electrodes, paving the way for more reliable and practical wearable EEG systems. By addressing key challenges in signal quality, we contribute to advancing long-term neurological monitoring technologies for real-world applications

With the growing demand for artificial intelligence (AI) and the Internet of Things (IoT), there is an increasing need for smart vision sensors and cameras with energy-efficient computing capabilities. While previous works have explored in-sensor computing for feature extraction, they often rely on memory-based weight storage or fixed kernels, limiting their flexibility and energy efficiency. This paper introduces a low-power, programmable, memory-less convolution engine designed for feature extraction in the analog domain. The proposed engine utilizes a linear large-signal voltage-to-current converter-based Time-Domain (TD) multiply-accumulate (MAC) cell, employing time pulses as weights. A 32-phase subsampling phase-locked loop (SS-PLL) is implemented to generate 5-bit Time Domain weights for a programmable 3x3 kernel employed for feature extraction. The in-sensor convolution engine achieves an energy efficiency of 0.4 pJ/pixel at a data rate of 300 MSps, making it suitable for resource-constrained, battery-operated devices.

Unintended electromagnetic emissions, called EM emanations, can be exploited to recover sensitive information, posing security risks. Metal shielding, used by defense organizations to prevent data leakage, is costly and impractical for widespread use. This issue is particularly significant for IoT devices due to their sheer volume and varied deployment environments. Therefore, there is a research need for an automated detection method to monitor facilities and address data leakage promptly. To resolve this challenge, in the preliminary version of this work 1, a CNN-based detection method was proposed using HDMI cable emanations that provided ~95% accuracy up to 22.5m but had limitations due to training data. In this extended version, we augment the initial study by collecting and characterizing emanation data from IoT devices, everyday electronics, and cables. We propose a harmonic-based emanation detection method by developing a computational harmonic detection algorithm. The proposed method addresses the limitations of the CNN-based method and provides ~100% accuracy not only for HDMI emanation (compared to ~95% in the earlier CNN method) but also for all other tested devices and cables. Finally, it has also been tested in different environments to prove its efficacy in practical scenarios.

Recent expansions in multimedia devices for many applications, such as surveillance, self-driving cars, and healthcare, gather enormous amounts of real-time images for processing and inference. The images are first compressed using compression schemes, like joint photographics experts group (JPEG), before processing to reduce storage costs and additional power requirements for transmitting the captured data in this era of emerging ultra-wideband communication and human-body communication. The JPEG algorithm realizes image compression using simplistic matrix manipulations, making it preferable for hardware implementations. Furthermore, due to inherent error resilience and imperceptibility in images, JPEG can be approximated to reduce the required computation/processing power and area. This work demonstrates the first end-to-end approximation computing-based optimization of JPEG hardware using 1) an approximate division realized using bit-shift operators to reduce the complexity of the computationally intensive quantization block; 2) loop perforation; and 3) precision scaling on top of a multiplier-less fast discrete cosine transform (DCT) architecture to achieve an extremely energy-efficient JPEG compression unit which will be a perfect fit for power/bandwidth-limited scenario. Furthermore, a gradient descent-based heuristic composed of two conventional approximation strategies, i.e., precision scaling and loop perforation, is implemented for tuning the degree of approximation to tradeoff energy consumption with the quality degradation of the decoded image. The entire register-transfer level (RTL) design is coded in Verilog HDL, synthesized using the industry-standard tool, mapped to TSMC 65nm CMOS technology, and simulated using Cadence Spectre Simulator under 25 ° C, typical/typical (TT) corner. The approximate division approach in the quantization block achieved around 28% reduction in the active design area. The heuristic-based approximation technique combined with accelerator optimization achieves a significant energy reduction of 36% for a minimal image quality degradation of 2% sum of absolute difference (SAD). Simulation results also show that the proposed architecture consumes 15 uW at the DCT and quantization stages to compress a colored 480-p image at 6 frames/s.

Traditional deep learning models incur high computational overhead (approximately 1-30W) and are unsuitable for Ultra-Low-Power (ULP) wearable systems like smart glasses. In contrast, TinyML architectures are power-efficient but less accurate. We propose distributing a neural network (NN) between a ULP wearable node and a resource-rich hub to maintain high accuracy and low power consumption for applications like human-machine vision. Output features from the node are transmitted to the hub via low-power communication, where the remaining network runs on traditional GPUs. We introduce a Figure of Merit (FoM) to determine the optimal NN distribution point and a customized multiplier unit for ULP operation. Achieving ULP of 284μW and 9mW for different Autoencoder (AE) networks, our approach is 700× lower in power consumption compared to traditional GPU implementation.

The explosive surge in Human-AI interactions, fused with a soaring fascination in wearable technology, has ignited a frenzy of innovation and the emergence of a myriad of Wearable AI devices, each wielding diverse form factors, tackling tasks from health surveillance to turbocharging productivity. This paper delves into the vision for wearable AI technology, addressing the technical bottlenecks that stand in the way of its promised advancements.

The transition of data and clock signals between high and low states in electronic devices creates electromagnetic radiation according to Maxwell's equations. These unintentional emissions, called emanation, may have a significant correlation with the original information-carrying signal and form an information leakage source, bypassing secure cryptographic methods at both hardware and software levels. Information extraction exploiting compromising emanations poses a major threat to information security. Shielding the devices and cables along with setting a control perimeter for a sensitive facility are the most commonly used preventive measures. These countermeasures raise the research need for the longest detection range of exploitable emanation and the efficacy of commercial shielding. In this work, using data collected from 3 types of commercial HDMI cables (unshielded, single-shielded, and double-shielded) in an office environment, we have shown that the CNN-based detection method outperforms the traditional threshold-based detection method and improves the detection range from 4 m to 22.5 m for an iso-accuracy of ~ 95%. Also, for an iso-distance of 16 m, the CNN-based method provides ~ 100% accuracy, compared to ~ 88.5% using the threshold-based method. The significant performance boost is achieved by treating the FFT plots as images and training a residual neural network (ResNet) with the data so that it learns to identify the impulse-like emanation peaks even in the presence of other interfering signals. A comparison has been made among the emanation power from the 3 types of HDMI cables to judge the efficacy of multi-layer shielding. Finally, a distinction has been made between monitor contents, i.e., still image vs video, with an accuracy of 91.7% at a distance of 16 m. This distinction bridges the gap between emanation-based image and video reconstruction algorithms.

Traditional methods of repairing a broken cable focus on restoring electrical connectivity and mechanical integrity, ignoring the electromagnetic aspects of it. Most of these repairing methods create a small monopole antenna as a byproduct which affects its electromagnetic compatibility (EMC). Switching activity in the transmitted signal through the wire creates an unintentional emission, called emanation, according to Maxwell's equations. This emanation is usually weak and suppressed to conform to EMC requirements. However, the monopole antenna of the repaired cable helps transmit it better, increasing the SNR of the emanation and extending its detection range significantly. This creates a serious security issue as emanations contain a significant correlation with the source signal and can be exploited for information extraction. In this work, the electromagnetic aspects of the broken cable repairing process have been explored in detail. We have applied the most commonly used cable repairing methods (twisting, soldering, and butt connector) to 3 types of widely used cables (USB, power, and HDMI cable) which are broken intentionally for experimental purposes. Collected data shows that the emanation SNR increases significantly due to the repairing process with −47 dBm power at a 20 cm distance. Although emanation power varies from cable to cable, it remains detectable even at >4 m distances. This strong emanation can penetrate through obstacles and remain detectable up to ~1$\mathbf{m}$distance through a 14 cm thick concrete wall. Along with exploring the vulnerability, a possible remedy, external metal shielding, has been explored in detail. This work exposes a new dimension of information leakage.

Stochastic variation of process parameters within a die and technology-limitation-driven variation from die-to-die give rise to unique distribution patterns for manufacturing process parameters. These patterns work as a process signature that is transferred from the device level to the system level through electrical circuits and can be used to make a distinction among the processes. In this work, we propose an in-situ manufacturing process technology distinction method, radio frequency process specific functions (RF-PSFs), that uses process-specific inherent properties of an IC manifested in the transmitted radio frequency signal. Among many desirable testing criteria, RF-PSF addresses the question of fabrication with the intended process technology. This information plays an important role in modern zero-trust architecture and IC clone detection, a counterfeiting method where the IC is manufactured using a different process. An RF transmitter with RF-DAC power amplifier for QPSK modulation has been designed and simulated in 14, 22, and 65 nm processes for five process corners (TT, FF, FS, SF, and SS) in Cadence. The simulated data have been processed in MATLAB. A multilayer perceptron (MLP), trained with the constellation data, provides an average accuracy of${\sim }90\%$for process distinction. Realizing that: 1) a higher order modulation will have even more process information and 2) we can harness the convolutional neural network’s (CNNs) improved capability on pattern recognition, we can feed image-like constellation plots to a CNN to get better and consistent performance. Using the baseband constellations for 64-QAM modulated data as images, we have achieved${\sim }100\%$accuracy with commonly used, pretrained CNN models (ResNet18, ResNet50, and GoogleNet) through transfer learning. The separation among five process corners within a process, termed intraprocess variation, is also analyzed. The effect of baseband sampling rate and ADC resolution, two practical limitations in RF systems, have been explored. An extensive study has been performed on the effect of a key design parameter at the RF circuit level, i.e., W/L or aspect ratio, leading to design insights, proper CNN selection, and some control parameters. This work establishes RF-PSF as a zero-power, zero-area overhead, and in-situ process distinction method.

While cryptographic implementations provide computational security in circuits and systems, hardware attack techniques, e.g., electromagnetic (EM) side-channel analysis (SCA) attack can still break through. The commonplace countermeasures for EM SCA attack require significant overheads in terms of power consumption. This article explores an on-chip capacitive sensing technique for the purpose of detection of an approaching EM probe even before an attack is performed, thereby alleviating the overheads incurred by any countermeasure against such attacks. Different type of capacitive structures are considered in regards to sensitivity and area. The proposed method of coplanar capacitive asymmetry sensing (CEASE) consists of a grid of four metal plates of the same size and dimensions determined through design space exploration. A comparison between the capacitive and inductive sensing technique is also performed in terms of detection range through theoretical arguments and EM simulation. A$>$17% change in capacitance is shown at a distance of 1 mm, implying a$>10\times $improvement in the detection range over inductive sensing methods. Furthermore, at 0.1-mm distance, a$>$45% change in capacitance is observed, leading to a$>3\times $and$>11\times $sensitivity improvement over capacitive parallel plate sensing and inductive sensing, respectively.

This work presents an interference-adaptive Gallium Nitride (GaN) low-noise amplifier (LNA) front-end with orthogonal frequency and linearity tuning for applications in communication base stations, radar and electronic warfare (EW). The system operates between 2–6 GHz and provides a sub 5 ms tuning time for an input power tuning range of 40 dB. The orthogonal tuning consists of two phases: 1. frequency tuning with four tunable bandpass and bandstop filters for interference rejection, 2. linearity tuning with a combination of coarse tuning through look-up table (LUT) and fine-tuning through incremental adaptation to trade off power with linearity. GaN LNA’s linearity can be adjusted between P textsubscript 1dB,IN = -10 and 1.5 dBm with output P textsubscript 1dB up to 25 dBm (11.5 dB range) with the LNA power changing from 500 mW to 2 W (x4 increase). The average LNA power with orthogonal frequency and linearity tuning decreases by 56% as compared with the system operating at the worst-case no tuning condition. Two systems involving commercial filters and custom cavity resonator-based filters were constructed. The filters further increase the system P textsubscript 1dB,IN by the filter rejection of the interference signal. The rest of the controls consume about 10% of the worst-case condition LNA power.

Securing ICs are becoming increasingly challenging with rapid improvements in electromagnetic (EM) side-channel analysis (SCA) and fault injection (FI) attacks. In this work, we develop a pro-active approach to detect and counter these attacks by embedding a single on-chip integrated loop around a crypto core (AES-256), designed and fabricated using TSMC 65nm process. The measured results demonstrate that the proposed system 1) provides EM-Self-awareness by acting as an on-chip H-field sensor, detecting voltage/clock glitching fault-attacks; 2) senses an approaching EM probe to detect any incoming threat; and 3) can be used to induce EM noise to increase resilience against EM attacks. This work combines EM analysis, ML based secured system and shows the efficacy by measurements from custom-built 65nm CMOS IC.

Intensive research on energy-harvested sensor nodes has been driven by the challenges in achieving stringent design goals of battery lifetime, information accuracy, transmission distance, and cost. This challenge is further amplified by the inherent power-intensive nature of long-range communication when sensor networks are required to span vast areas, such as agricultural fields and remote terrain. Solar power is a common energy source in wireless sensor nodes, however, it is not reliable due to fluctuations in available power stemming from the changing seasons and weather conditions. This article tackles these issues by presenting a perpetually powered, energy-harvesting sensor node which utilizes a minimally sized solar cell and is capable of long-range communication by dynamically co-optimizing energy consumption and information transfer, termed as energy-information dynamic co-optimization (EICO). This energy-information intelligence is achieved by adaptive dutycycling of information transfer based on the total amount of energy available from the harvester and charge storage element to optimize the energy consumption of the sensor node, while employing in-sensor analytics (ISA) to minimize loss of information. This is the first reported sensor node1 km at continuous information transfer rates of up to 1 packet/second which is enabled by EICO and ISA.

This work presents a Cross-device Deep-Learning based Electromagnetic (EM-X-DL) side-channel analysis (SCA) on AES-128, in the presence of a significantly lower signal-to-noise ratio (SNR) compared to previous works. Using a novel algorithm to intelligently select multiple training devices and proper choice of hyperparameters, the proposed 256-class deep neural network (DNN) can be trained efficiently utilizing pre-processing techniques like PCA, LDA, and FFT on measurements from the target encryption engine running on an 8-bit Atmel microcontroller. In this way, EM-X-DL achieves >90% single-trace attack accuracy. Finally, an efficient end-to-end SCA leakage detection and attack framework using EM-X-DL demonstrates high confidence of an attacker with <20 averaged EM traces.

This work presents a white-box modeling of the electromagnetic (EM) leakage from an integrated circuit (IC) to develop EM side-channel analysis (SCA)-aware design techniques. A new digital library cell layout design technique is proposed to minimize the EM leakage and is evaluated using a high-frequency structure simulator (HFSS)-based framework. Backed by our physics-based understanding of EM radiation, the proposed double-row power grid-based digital cell layout design shows$>5\times $reduction in the EM SCA leakage compared to the traditional digital logic gate layout design. Furthermore, exploiting the magneto-quasistatic (MQS) regime of operation of the EM leakage from the CMOS circuits, the HFSS-based framework is utilized to develop a pre-silicon (Si) EM SCA evaluation technique to assess the vulnerability of cryptographic implementations against such attacks during the design phase itself.

Neuromorphic Computing has become tremendously popular due to its ability to solve certain classes of learning tasks better than traditional von-Neumann computers. Data-intensive classification and pattern recognition problems have been of special interest to Neuromorphic Engineers, as these problems present complex use-cases for Deep Neural Networks (DNNs) which are motivated from the architecture of the human brain, and employ densely connected neurons and synapses organized in a hierarchical manner. However, as these systems become larger in order to handle an increasing amount of data and higher dimensionality of features, the designs often become connectivity constrained. To solve this, the computation is divided into multiple cores/islands, called processing engines (PEs). Today, the communication among these PEs are carried out through a power-hungry network-on-chip (NoC), and hence the optimal distribution of these islands along with energy-efficient compute and communication strategies become extremely important in reducing the overall energy of the neuromorphic computer, which is currently orders of magnitude higher than the biological human brain. In this paper, we extensively analyze the choice of the size of the islands based on mixed-signal neurons/synapses for 3-8 bit-resolution within allowable ranges for system-level classification error, determined by the analog non-idealities (noise and mismatch) in the neurons, and propose strategies involving local and global communication for reduction of the system-level energy consumption. AC-coupled mixed-signal neurons are shown to have 10X lower non-idealities than DC-coupled ones, while the choice of number of islands are shown to be a function of the network, constrained by the analog to digital conversion (or viceversa) power at the interface of the islands. The maximum number of layers in an island is analyzed and a global bus-based sparse connectivity is proposed, which consumes orders of magnitude lower power than the competing powerline communication techniques.

Over the last decade, the growing influence of open source software has necessitated the need to reduce the abstraction levels in hardware design. Open source hardware significantly reduces the development time, increasing the probability of first-pass success and enable developers to optimize software solutions based on hardware features, thereby reducing the design costs. The recent introduction of open source Process Development Kit (OpenPDK) by Skywater technologies in June 2020 has eliminated the barriers to Application-Specific Integrated Circuit (ASIC) design, which is otherwise considered expensive and not easily accessible. The OpenPDK is the first concrete step towards achieving the goal of open source circuit blocks that can be imported to reuse and modify in ASIC design. With process technologies scaling down for better performance, the need for entirely digital designs, which can be synthesized in any standard Automatic Place-and-Route (APR) tool, has increased considerably, for mapping physical design to the new process technology. This work presents a first open source all-digital Serializer/Deserializer (SerDes) for multi-GHz serial links designed using Skywater OpenPDK 130nm process node. To ensure that the design is fully synthesizable, the SerDes uses CMOS inverter based drivers at the transmitter, while the receiver front end comprises a resistive feedback inverter as a sensing element, followed by sampling elements. A fully digital oversampling CDR at the receiver end recovers the transmitter clock for proper decoding of data bits. The physical design flow utilizes OpenLANE, which is an open source end-to-end tool for generating GDS from RTL. Cadence Virtuoso has been used for extracting parasitics for post-layout simulations, which exhibit the SerDes functionality at 2 Gbps for 34 dB channel loss while consuming 438 mW power. The generated GDS and netlist files of the SerDes, along with the required documentation, are uploaded in a GitHub repository for public access.

Electromagnetic (EM) side-channel analysis (SCA) attack, which breaks cryptographic implementations, has become a major concern in the design of circuits and systems. This paper focuses on EM SCA and proposes the detection of an approaching EM probe even before an attack is performed. The proposed method of co-planar capacitive asymmetry sensing consists of a grid of four metal plates of the same size and dimension. As an EM probe approaches the sensing metal plates, the symmetry of the sensing metal plate system breaks, and the capacitance between each pair diverge from their baseline capacitances. Using Ansys Maxwell Finite Element Method (FEM) simulations, we demonstrate that the co-planar capacitive asymmetry sensing has an enhanced detection range compared to other sensing methods. At a distance of 1 mm between the sensing metal plates and the approaching EM probe, it shows >17 % change in capacitance, leading to a > 10 × improvement in detection range over the existing inductive sensing methods. At a distance of 0.1 mm, a > 45% change in capacitance is observed, leading to a > 3 × and > 11 × sensitivity improvement over capacitive parallel sensing and inductive sensing respectively. Finally, we show that the co-planar capacitive asymmetry sensing is sensitive to both E-field and H-field probes, unlike inductive sensing which cannot detect an E-field probe.

An adversary can exploit side-channel information such as power consumption, electromagnetic (EM) emanations, acoustic vibrations or the timing of encryption operations to derive the secret key from an electronic device. Signature aTtenuation Embedded CRYPTO with Low-Level metAl Routing (STELLAR) is a technique to mitigate power and EM-based attacks, however, it incurs 50% power overhead. This work presents iSTELLAR, which reduces the power overhead by operating STELLAR intermittently utilizing an intelligent scheduling algorithm. The proposed scheduling algorithm for iSTELLAR determines the optimal locations during the crypto operation to turn STELLAR ON, and thereby reduces the power overhead by$> 30\%$compared to the normal STELLAR operation, while eliminating the information leakage.

Unlike traditional radio frequency device authentication which utilizes security keys in conjunction with a digital subsystem for verification, human voice communication involves probabilistic identification of a person based on his/her voice signatures and improves the detection probability over time. Inspired by voice-based human identification, we implement a novel method of augmenting trust during device detection and authentication, involving dynamic irregular clustering which exploits the unique nonidealities in IoT devices as physical signatures originated from Radio Frequency (RF) circuitry. The proposed method increases the confidence level of the classification as more data come in from a particular device, and is also able to detect new devices that do not fall into any of the previous clusters. Using 30 Xbee modules as transmitters, we show that our proposed method can detect a transmitter with > 95% sensitivity 100% with optimum parameters) using only 0.2 milliseconds of test data which makes it suitable for a very low latency communication system. Also, the incremental learning feature of the proposed method renders a gradual increase in sensitivity as more data are available from the transmitter end. The proposed method can provide an additional security layer in conjunction with the existing methods without adding any additional burden, which is extremely important for resource-limited asymmetric IoT nodes.

In this paper, we present the design considerations for a sub-25μW phase-locked loop (PLL) with a wide tuning range and multi-phase outputs, which makes it suitable for applications that involve clock-and-data-recovery with variable data rates, such as broadband body-area-networks. Several architectures for the voltage- controlled-oscillator (VCO) are analyzed for power and performance, and the considerations for keeping the VCO's low-dropout-regulator (LDO) within the loop and outside the loop are discussed. Power consumption is minimized by keeping the LDO outside the loop, which exempts the error-amplifier (EA) from the bandwidth constraints posed by the PLL. Conforming to the analysis, the PLL is designed and simulated in a standard 65nm CMOS process, and the results show that energy-efficiencies as low as 70fJ/cycle can be achieved with a tuning range of 1-450MHz along with multi-phase outputs with RMS timing jitter of 11.4ps (frequency offset <; 100ppm) from a 31-stage split-tuned ring oscillator VCO.

Electromagnetic (EM) side-channel analysis (SCA) attack, which breaks cryptographic implementations, has become a major concern in the design of circuits and systems. This paper presents the design and analysis of the EM side-channel attack detection system utilizing patterned-ground co-planar capacitive asymmetry sensing (PG-CAS) for approaching probe, targeting to improve sensitivity, detection range, and power consumption compared to LC oscillator utilizing inductive sensing. The PG-CAS consists of a grid of four metal plates of the same size at the top metal layer and a patterned ground plane at a lower metal. As an EM probe approaches, electric field lines between the plates and plate-ground get distorted, thereby breaking the symmetry of the inter-plate and the plate-ground capacitance system and this change in capacitance is sensed. The PG-CAS circuit consists of two LC oscillators, mixer, low pass filter (LPF), resistive feedback amplifier (RFA) and a digital logic. By down-converting sensing signal to low-frequency using mixer, LPF, RFA and digital logic, the detection range is significantly improved. At a distance of 1 mm between the sensing metal plates and the approaching EM probe, system-level simulation results using TSMC 65nm technology and Ansys Maxwell show a > 10% change in the output frequency from the baseline frequency, leading to a > 10× improvement in the detection range and a ~ 3× improvement in power consumption over existing inductive sensing methods.

Decades of continuous scaling has reduced the energy of unit computing to virtually zero, while energy-efficient communication has remained the primary bottleneck in achieving fully energy-autonomous Internet-of-Things (IoT) nodes. This article presents and analyzes the tradeoffs between the energies required for communication and computation in a wireless sensor network, deployed in a mesh architecture over a 2400-acre university campus, and is targeted toward multisensor measurement of temperature, humidity and water nitrate concentration for smart agriculture. Several scenarios involving in-sensor analytics (ISA), collaborative intelligence (CI), and context-aware switching (CAS) of the cluster head during CI has been considered. A real-time co-optimization algorithm has been developed for minimizing the energy consumption in the network, hence maximizing the overall battery lifetime. Measurement results show that the proposed ISA consumes ≈ 467× lower energy as compared to traditional Bluetooth low energy (BLE) communication, and ≈ 69500× lower energy as compared with long-range (LoRa) communication. When the ISA is implemented in conjunction with LoRa, the lifetime of the node increases from a mere 4.3 h to 66.6 days with a 230-mAh coin cell battery, while preserving >99% of the total information. The CI and CAS algorithms help in extending the worst case node lifetime by an additional 50%, thereby exhibiting an overall network lifetime of ≈ 104 days, which is >90% of the theoretical limits as posed by the leakage current present in the system, while effectively transferring information sampled every second. A Web-based monitoring system was developed to continuously archive the measured data, and for reporting real-time anomalies.

Human Body Communication has shown great promise to replace wireless communication for information exchange between wearable devices of a body area network. However, there are very few studies in literature, that systematically study the channel loss of capacitive HBC for wearable devices over a wide frequency range with different terminations at the receiver, partly due to the need for miniaturized wearable devices for an accurate study. This paper, for the first time, measures the channel loss of capacitive HBC from 100KHz to 1GHz for both high-impedance and 50Ω terminations using wearable, battery powered devices; which is mandatory for accurate measurement of the HBC channel-loss, due to ground coupling effects. Results show that high impedance termination leads to a significantly lower channel loss (40 dB improvement at 1MHz), as compared to 50Ω termination at low frequencies. This difference steadily decreases with increasing frequency, until they become similar near 80MHz. Beyond 100MHz inter-device coupling dominates, thereby preventing accurate measurements of channel loss of the human body. The measured results provide a consistent wearable, wide-frequency HBC channel loss data and could serve as a backbone for the emerging field of HBC by aiding in the selection of an appropriate operation frequency and termination.

Communication during touch provides a seamless and natural way of interaction between humans and ambient intelligence. Current techniques that couple wireless transmission with touch detection suffer from the problem of selectivity and security, i.e., they cannot ensure communication only through direct touch and not through close proximity. We present BodyWire-HCI , which utilizes the human body as a wire-like communication channel, to enable human–computer interaction, that for the first time, demonstrates selective and physically secure communication strictly during touch. The signal leakage out of the body is minimized by utilizing a novel, low frequency Electro-QuasiStatic Human Body Communication (EQS-HBC) technique that enables interaction strictly when there is a conductive communication path between the transmitter and receiver through the human body. Design techniques such as capacitive termination and voltage mode operation are used to minimize the human body channel loss to operate at low frequencies and enable EQS-HBC. The demonstrations highlight the impact of BodyWire-HCI in enabling new human–machine interaction modalities for variety of application scenarios such as secure authentication (e.g., opening a door and pairing a smart device) and information exchange (e.g., payment, image, medical data, and personal profile transfer) through touch (https://www.youtube.com/watch?v=Uwrig2XQIH8).

This article, for the first time, demonstrates Cross-device Deep Learning Side-Channel Attack (X-DeepSCA), achieving an accuracy of > 99.9%, even in presence of significantly higher inter-device variations compared to the inter-key variations. Augmenting traces captured from multiple devices for training and with proper choice of hyper-parameters, the proposed 256-class Deep Neural Network (DNN) learns accurately from the power side-channel leakage of an AES-128 target encryption engine, and an N-trace (N ≤ 10) X-DeepSCA attack breaks different target devices within seconds compared to a few minutes for a correlational power analysis (CPA) attack, thereby increasing the threat surface for embedded devices significantly. Even for low SNR scenarios, the proposed X-DeepSCA attack achieves ~ 10× lower minimum traces to disclosure (MTD) compared to a traditional CPA.

Traditional authentication in radio-frequency (RF) systems enable secure data communication within a network through techniques such as digital signatures and hash-based message authentication codes (HMAC), which suffer from key-recovery attacks. State-of-the-art Internet of Things networks such as Nest also use open authentication (OAuth 2.0) protocols that are vulnerable to cross-site-recovery forgery (CSRF), which shows that these techniques may not prevent an adversary from copying or modeling the secret IDs or encryption keys using invasive, side channel, learning or software attacks. Physical unclonable functions (PUFs), on the other hand, can exploit manufacturing process variations to uniquely identify silicon chips which makes a PUF-based system extremely robust and secure at low cost, as it is practically impossible to replicate the same silicon characteristics across dies. Taking inspiration from human communication, which utilizes inherent variations in the voice signatures to identify a certain speaker, we present RF-PUF: a deep neural network-based framework that allows real-time authentication of wireless nodes, using the effects of inherent process variation on RF properties of the wireless transmitters (Tx), detected through in-situ machine learning at the receiver (Rx) end. The proposed method utilizes the already-existing asymmetric RF communication framework and does not require any additional circuitry for PUF generation or feature extraction. The burden of device identification is completely shifted to the gateway Rx, similar to the operation of a human listener's brain. Simulation results involving the process variations in a standard 65-nm technology node, and features such as local oscillator offset and I-Q imbalance detected with a neural network having 50 neurons in the hidden layer indicate that the framework can distinguish up to 4800 Tx(s) with an accuracy of 99.9% [≈99% for 10000 Tx(s)] under varying channel conditions, and without the need for traditional preambles. The proposed scheme can be used as a stand-alone security feature, or as a part of traditional multifactor authentication.

Neuromorphic computing (NC) has acquired tremendous interest because of its ability to overcome the limitations of von-Neumann systems in data-intensive applications. NC systems are inspired from the human brain, which combine storage (synapse) and compute (neuron) to circumvent the memory bottlenecks in von-Neumann computing. The human brain consists of densely connected neurons, where each neuron can connect to thousands of synapses. Such dense connectivity enables hierarchical learning that enables high classification accuracies in NC systems, such as spiking neural networks (SNNs). Past research has focused on many-core architectures that implement synapses with memristive crossbars to overcome the memory bottlenecks and enable efficient compute. However, mimicking brainlike connectivity poses significant challenges. This is because the typical computation cores in a many-core architecture are connected with network-on-chip (NOC), which have high power consumption. In this paper, we propose a power line communication (PLC)-based architecture built with memristive crossbars for SNNs. PLC can use the on-chip power lines augmented with low-overhead transceiver to communicate data between neurons efficiently. Hence, PLC can enable dense connectivity required in SNNs while preserving the efficiency of memristive crossbars. We perform evaluations on SNNs ranging in scale from 1to 10 M synapses to demonstrate the efficiency of PLC-based NC system. We also propose a hybrid PLC-NOC-based design which can achieve high throughput along with high energy efficiency.

Neuromorphic computing, inspired by the brain, promises extreme efficiency for certain classes of learning tasks, such as classification and pattern recognition. The performance and power consumption of neuromorphic computing depend heavily on the choice of the neuron architecture. Digital neurons (Dig-N) are conventionally known to be accurate and efficient at high speed while suffering from high leakage currents from a large number of transistors in a large design. On the other hand, analog/mixed-signal neurons (MS-Ns) are prone to noise, variability, and mismatch but can lead to extremely lowpower designs. In this paper, we will analyze, compare, and contrast existing neuron architectures with a proposed MS-N in terms of performance, power, and noise, thereby demonstrating the applicability of the proposed MS-N for achieving extreme energy efficiency (femtojoule/multiply and accumulate or less). The proposed MS-N is implemented in 65-nm CMOS technology and exhibits >100× better energy efficiency across all frequencies over two traditional Dig-Ns synthesized in the same technology node. We also demonstrate that the inherent error resiliency of a fully connected or even convolutional neural network can handle the noise as well as the manufacturing nonidealities of the MS-N up to certain degrees. Notably, a system-level implementation on CIFAR-10 data set exhibits a worst case increase in classification error by 2.1% when the integrated noise power in the bandwidth is ~ 0.1 μ V2, along with ±3σ amount of variation and mismatch introduced in the transistor parameters for the proposed neuron with 8-bit precision.

Power side-channel analysis (SCA) has been of immense interest to most embedded designers to evaluate the physical security of the system. This work presents profiling-based cross-device power SCA attacks using deep-learning techniques on 8-bit AVR microcontroller devices running AES-128. First, we show the practical issues that arise in these profiling-based cross-device attacks due to significant device-to-device variations. Second, we show that utilizing principal component analysis (PCA)-based preprocessing and multidevice training, a multilayer perceptron (MLP)-based 256-class classifier can achieve an average accuracy of 99.43% in recovering the first keybyte from all the 30 devices in our data set, even in the presence of significant interdevice variations. Results show that the designed MLP with PCA-based preprocessing outperforms a convolutional neural network (CNN) with four-device training by ~20% in terms of the average test accuracy of cross-device attack for the aligned traces captured using the ChipWhisperer hardware. Finally, to extend the practicality of these cross-device attacks, another preprocessing step, namely, dynamic time warping (DTW) has been utilized to remove any misalignment among the traces, before performing PCA. DTW along with PCA followed by the 256-class MLP classifier provides ≥10.97% higher accuracy than the CNN-based approach for cross-device attack even in the presence of up to 50 time-sample misalignments between the traces.

In a world connected by Internet of Things (IoT), sensor nodes play a vital role in monitoring, transmitting and processing useful data. In this session, we will discuss about four significant aspects of intelligent sensor nodes.

Connected smart wearable devices are becoming increasingly popular with the advent of cheap, miniaturized, ultra-low-power computing and communication. Human Body Communication (HBC) is emerging as an alternative to Wireless Body Area Network (WBAN) for communication among these devices, as it provides higher energy-efficiency and security. One of the biggest bottleneck of HBC is the interference picked up due to the human body antenna effect, with Signal to Interference Ratio often worse than -20dB. An interference robust integrating dual data rate (DDR) receiver is introduced which can adapt itself to changing interference conditions and provide high interference rejection by Pulse Width Modulation of integration clock, thus dynamically changing its duty cycle. The theory, architecture of the receiver is developed along with the adaptation algorithm to train the receiver to find the optimum duty cycle of operation. System-level simulations show >20 dB of rejection even in presence of variable interference frequencies.

Continuous miniaturization and cost reduction of unit computing has led to the prolific growth of smart wearable devices. These devices, present on and around the human body, form a complex network known as the Human-Intranet. The Human-Intranet is typically connected through Wireless Body Area Network (WBAN). However, Human Body Communication (HBC) has recently emerged as an energy-efficient and secure alternative that uses the human body as the communication medium. Human-human, human-machine interaction creates dynamic HBC channels, which allow these Human-Intranets to interact with each other forming a Human-Internet. In this paper, we present the concept and demonstration of Secure Human-Internet using dynamic HBC. We highlight important applications of Human-Internet and discuss the architecture of a wearable Human-Internet device capable of communicating through inter-body dynamic HBC. A custom-built hardware prototype is used to demonstrate for the first time information exchange (e.g. business card) during handshaking. Dynamic signal transfer characteristics during inter-body communication through handshake between two individuals wearing such devices are measured and analyzed. The effects of data transmission rate, handshake posture on the HBC based inter-body communication is explored to demonstrate its effectiveness and limitations under varying realistic scenarios. The specific COTS based HBC implementation shows > 8× better energy efficiency compared to the Bluetooth implementation.

This article presents a Built-in self-test (BIST) solution for polar transceivers with low cost and high accuracy. Radio frequency (RF) Polar transceivers are desirable for portable devices due to higher power efficiency compared to traditional RF Cartesian transceivers. Unfortunately, their design is quite challenging due to substantially different signal paths that need to work coherently to ensure signal quality. In the receiver, phase and gain mismatches degrade sensitivity and error vector magnitude. In the transmitter, delay skew between the envelope and phase signals and the finite envelope bandwidth can create intermodulation distortion, which leads to violation of spectral mask requirements. Typically, these parameters are not directly measured but calibrated through spectral analysis using expensive RF equipment, leading to lengthy and costly measurement/calibration cycles. However, characterization and calibration of these parameters with analytical model would reduce the test time and cost considerably. In this article, we propose a technique to measure with the intent to calibrate impairments of the polar transceiver in the loop-back mode. Simulation and hardware measurement results show that the proposed technique can characterize the targeted impairments accurately.

The widespread proliferation of sensor nodes in the era of Internet of Things (IoT) coupled with increasing sensor fidelity and data-acquisition modality is expected to generate 30+ Exabytes of data per month by 2020. In this data driven IoT world, wireless communication is a significant consumer of energy, and paying careful attention to the balance between local and remote computation is critical to overall energy usage. The communication fabrics that will handle this enormous amount of IoT workload will need to be energy-efficient under changing contexts such as channel conditions, applications, QoS, data-rate requirements etc. Moreover, the IoT devices will often include multiple parallel communication fabrics; e.g. wired, proximity, mm-wave, 5G etc. We will discuss how self-learning can enable context-aware operation in such communication systems to allow minimum energy/bit and energy/information for any given communication scenario. The need for context-aware operation within and among multiple physical layers (PHYs) in future IoT workloads will be highlighted. Such energy-efficient communication (Shannon's Law) along with low-power computing (Moore's Law), is expected to harness the true potential of the IoT revolution and produce dramatic societal impact.

With the advent of cheap computing through five decades of continued miniaturization following Moore's Law, wearable devices are becoming increasingly popular. These wearable devices are typically interconnected using wireless body area network (WBAN). Human body communication (HBC) provides an alternate energy-efficient communication technique between on-body wearable devices by using the human body as a conducting medium. This allows order of magnitude lower communication power, compared to WBAN, due to lower loss and broadband signaling. Moreover, HBC is significantly more secure than WBAN, as the information is contained within the human body and cannot be snooped on unless the person is physically touched. In this paper, we highlight applications of HBC as (1) Social Networking (e.g. LinkedIn/Facebook friend request sent during Handshaking in a meeting/party), (2) Secure Authentication using human-human or human-machine dynamic HBC and (3) ultra-low power, secure BAN using intra-human HBC. One of the biggest technical bottlenecks of HBC has been the interference (e.g. FM) picked up by the human body acting like an antenna. In this work for the first time, we introduce an integrating dual data rate (DDR) receiver technique, that allows notch filtering (>20 dB) of the interference for interference-robust HBC.

In this paper, a novel built-in tuning technique to compensate for process variability-induced imperfections in RF circuits is proposed. The yield improvement methodology proposed is a generic and self-contained tuning method that does not require a digital signal processor as in prior software-based methods or the use of a tester. The technique uses digital logic that can be synthesized on-chip along with the analog/RF tuning circuitry to performing self-tuning. An optimized digital bitstream (stimulus) is used to stimulate the RF device, and the response of the device is downconverted to the low-frequency domain using a sensor. The resulting signal is mapped to a digital signature, in such a way that the Hamming distance between the observed and the reference signatures represents the degree by which the device specifications differ from the nominal specifications. A logic-driven algorithm is used to minimize this Hamming distance to optimize multiple RF specifications concurrently. The presented methodology incurs minimal area overhead, and the tuning time is in the order of milliseconds. Results obtained by tuning the power amplifier of a 2.4-GHz transmitter show up to 16% yield improvement. To validate the proposed yield improvement concept on hardware, results obtained from experimentation on an industrial transmitter are presented.

Real-time systems for wireless communication, digital signal processing and control experience a wide gamut of operating conditions (signal/channel noise, workload demand, perturbed process conditions). As device bandwidths expand, it becomes increasingly expensive, from a power consumption and reliability perspective, to operate such real-time systems for worst-case (static) performance requirements. In contrast, it is attractive to design algorithms, architectures and circuits that are power-performance tunable and can adapt dynamically, via self-learning techniques, to the requirements of system-level applications for extended battery usage and device lifetime. Such future systems will feed application level demands to the underlying algorithm-architecture-circuit design fabric through built-in sense-and-control infrastructure (hardware, software). The sense functions assess instantaneous application level demands (e.g. throughput, signal integrity) as well as the performances of the individual hardware components as determined by manufacturing process conditions. The control functions actuate algorithm-through-circuit level tuning knobs that continuously trade off performance vs. power of the individual software and hardware modules in such a way as to deliver the end-to-end desired application level Quality of Service (QoS), while minimizing energy/power consumption. Application to wireless communications systems, digital signal processing and control algorithms is discussed.

Modern radio front ends are required to operate over diverse channel conditions requiring the incorporation of significant performance overheads into their design. This results in significantly higher power consumption over most of the operational period since the worst case channels are not statistically prevalent. Adaptive systems solve this problem by adapting the performance and power consumption depending on channel conditions. In this paper, it is demonstrated that depending upon the throughput requirements of the system multiple low-power adaptation modes can be designed. These modes ensure either highest throughput operation or lowest energy-per-bit operation. The operation of these modes is demonstrated in simulation using multiple-input-multiple-output (MIMO) receiver and transmitter front ends. Subsequently, the concepts are demonstrated in hardware for both MIMO and single-input-single-output front ends.

This paper presents a Built-in self-test (BIST) solution for polar transmitters with low cost. Polar transmitters are desirable for portable devices due to higher power efficiency they provide compared to traditional Cartesian transmitters. However, they generally require iterative test/measurement/calibration cycles. The delay skew between the envelope and phase signals and the finite envelope bandwidth can create intermodulation distortion (IMD) that leads to the violation of the spectral mask and error vector magnitude (EVM) requirements. Typically, these parameters are not directly measured but calibrated through spectral performance analysis using expensive RF equipment, leading to lengthy and costly measurement/calibration cycles. Characterization and calibration of these parameters inside the device would reduce the test time and cost considerably. In this paper, we propose a technique to measure the delay skew and the finite envelope bandwidth, two parameters that can be digitally calibrated, based on the measurement of the output of the receiver in the loop-back mode. Simulation and hardware measurement results show that the proposed technique can characterize the targeted impairments in the polar transmitter accurately.

Prior research has established that dynamically trading-off the performance of the RF front-end for reduced power consumption across changing channel conditions, using a feedback control system that modulates circuit and algorithmic level "tuning knobs" in real-time, leads to significant power savings. It is also known that the optimal power control strategy depends on the process conditions corresponding to the RF devices concerned. This complicates the problem of designing the feedback control system that guarantees the best control strategy for minimizing power consumption across all channel conditions and process corners. Since this problem is largely intractable due to the complexity of simulation across all channel conditions and process corners, we propose a self-learning strategy for adaptive MIMO-RF systems. In this approach, RF devices learn their own performance vs. power consumption vs. tuning knob relationships "on-the-fly" and formulate the optimum reconfiguration strategy using neural-network based learning techniques during real-time operation. The methodology is demonstrated for a MIMO-RF receiver front-end and is supported by hardware validation leading to 2.5X power savings in minimal learning time.

Communication circuits/systems suffer from design margins required to support wide channel variations, increasing manufacturing process variations and multi-standard operation. Recent advances in channel and process adaptive communication systems, enabling zero-margin power-efficient operation and adaptive variation-tolerant self-healing systems enabling yield improvement are discussed.

This paper presents a process-variation tolerant, continuously channel-adaptive wireless front-end architecture and related adaptation algorithms to allow a radio-frequency transceiver to function with minimum power at all channel conditions and manufacturing process corner. Current wireless transceiver front-ends are designed for worst case channel conditions and a limited degree of post manufacture tuning is performed to compensate for process variations. It is shown how the proposed architecture can result in significant power savings over current practice without compromising system-level bit-error rate (while keeping the end-user experience unaffected). In contrast to traditional wireless circuits with limited tunability, such a zero-margin design is achieved by close loop adaptation of the wireless front-end circuits to ensure that they only consume the minimum power and deliver just enough performance (and not any more) for any channel condition. The adaptation methodology is applied to a WLAN receiver design and hardware measurement data for an adaptive receiver is presented showing a > 3 × power improvement under best case channel conditions.

Modern MIMO RF transceiver systems are designed to operate reliably under diverse channel conditions leading to incorporation of significant performance margins in RF transceiver systems. In general, across dynamically varying channel conditions, the fidelity of the RF front end devices can be traded-off against power consumption without compromising system-level BER limits. In this work such a real-time performance vs. power consumption modulation of RF front-end devices in MIMO systems is demonstrated. Through a multi-dimensional optimization technique, power-optimal configuration of the front-end for varying channel conditions are created. Additionally multiple low-power operating modes for the MIMO system are proposed depending on the performance metric (data rate or energy-per-bit) that need to be optimized for different applications.

A low cost methodology for simultaneous testing and tuning of multiple chains of MIMO-OFDM wireless transmitter for system-level specifications is presented. Bandwidth-partitioned test stimuli enable the determination of the behavioral characteristics of the different chains of the RF transmitter using a one-time data acquisition. The determined behavioral characteristics of the transmitters are then correlated to system-level specifications in the simulation environment. Using the test setup, a power conscious system-level tuning approach for yield improvement is developed for tuning of parametric deviations. A yield improvement of 20% is obtained using the proposed methodology. Finally, an adaptive tuning approach is presented for those devices that face increased reliability risks/power-budget violations due to the excessive power consumption caused by post-manufacturing tuning. The tuning methodology achieves new performance metrics for these devices that attempt to maximize the conditions under which the device operates. Significant improvement in yield is obtained using the adaptive tuning methodology. Preliminary hardware validation of the proposed methodology using off the shelf components is performed.

Polar transmitters are desirable for portable devices due to higher power efficiency they provide compared to traditional Cartesian transmitters. However, the difference in architecture results in differences in potential circuit impairments/fault models, leading to different test/measurement/calibration requirements. The delay skew between the envelope and phase signals and the finite envelope bandwidth can create inter modulation distortion that leads to the violation of the spectral mask and error vector magnitude (EVM) requirements. Therefore, measurement and compensation/calibration of these parameters are important to ensure proper operation for the polar transmitter. In this paper, we propose a technique to measure the delay skew and the finite envelope bandwidth based on the measurement of the 3rdorder inter modulation distortion (IMD3) at the output of the transmitter. First, a two-tone input at a sufficiently low frequency is applied to the transmitter baseband input to calculate the delay. Then, we apply another two-tone input at a relatively higher frequency to determine the envelope bandwidth. Simulation and hardware measurement results show that the proposed technique can characterize the targeted impairments in the polar transmitter accurately within 10ms which is negligible compared to signal source switching and settling times.

Testing of adaptive analog/RF systems is challenging as any test procedure must ensure that the system adapts correctly to external perturbations (process, workload) without incurring the excessive test time associated with iterative tuning procedures. This problem is made worse by the increased number of adaptation settings (“tuning knob values”) and the requirement of measuring specifications at all of these settings. In this paper, a new test technique is proposed that allows the closed loop performance of the adaptation procedure to be predicted from a set of open-loop tests. The optimal knob settings where the system should be tested in open-loop are found using a gradient based search algorithm and optimized test signals are generated such that the error in performance prediction across different tuning knob settings is minimized. The results of these tests are then mapped to the performance of the adaptive system which is validated implicitly without incurring large testing and tuning costs. Simulation results and hardware measurement results prove the validity of the proposed technique.

Earlier research has demonstrated that the power in a RF front-end can be traded off for performance in real-time to operate at the threshold of acceptable operation using a lookup table driven controller. Such a controller needs careful calibration and suffers from modeling inaccuracies which must be guardbanded during real-time operation resulting in "less than optimal" power consumption. In this work we propose a real time fuzzy noise-distortion control algorithm for low-power adaptation of the RF front-end to continuously changing channel conditions. As opposed to prior techniques, the proposed control algorithm handles adaptation to channel attenuation and fading as well as in-band and out- of- band interference, taking advantage of signal and interferer estimation techniques that are already incorporated in modern transceivers. In the proposed technique, the RF front-end controller automatically finds an optimal power-performance trade-off point in real-time across a large gamut of channel conditions. It is seen that about 23% savings in power consumption can be obtained over RF systems that are not capable of real-time adaptation.

Error-vector-magnitude (EVM) is a system level specification that determines the overall modulation quality and exhibits strong correlation to the inherent nonidealities of a radio frequency (RF) system. In production testing, EVM tests incur significant cost due to the large number of symbols required to ensure test quality. In our approach, EVM is decomposed into its deterministic (due to static impairments: IQ mismatch, gain, AM-AM and AM-PM) and random (due to dynamic impairments: VCO phase noise, thermal noise) components. The static impairments are computed from the device under test (DUT) response to an optimized multitone test input. The dynamic impairments are computed using signal processing algorithms from the DUT test response to the same test input. The EVM of the RF system is then derived from the computed static and dynamic impairments, respectively. Experimental results show that significant reduction in test time is possible without compromising EVM test quality.

This work develops a simple, practical yet easily realizable method for low cost measurement of phase and amplitude distortions in radio frequency power amplifiers (RF PA). Amplitude-to-amplitude (AM-AM) and amplitude-to-phase (AM-PM) distortions are two significant distortion effects in PAs at high output power levels, causing out of band interference in the transmitted signal and bit errors in the received signal. Traditional measurements of amplitude and phase distortion in RF PAs require the use of expensive vector network analyzers. In this work, we propose the use of phase-to-amplitude conversion to develop a low cost and accurate test methodology for AM-AM and AM-PM measurement using simple load board test circuitry along with software based difference generation and peak detection mechanisms. Using either simple sine wave stimulus with power sweep or a single amplitude modulated RF stimulus, both distortion effects can be measured with high accuracy for nominal devices as well as over process and voltage variations, while allowing significant reduction in test cost.

In wireless multimedia systems, significant power is consumed in processing image/video content This research looks specifically at the energy cost of wireless image/video transport focusing on image quality as an end metric. The quality of received image/video content depends on the effective bit error rate of the communication channel and the amount by which the image/video data is compressed prior to transmission. For a specified value of received signal quality (as determined by PSNR), the combination of the two that results in minimal RF energy consumption is first determined via an optimization procedure. Then across varying channel conditions, the baseband signal is companded and power is saved by re-biasing the RF power amplifier (PA), while maintaining the "optimal" transmission bit error rate value determined in the first step. Closed loop feedback control is used to guarantee that the received image/video quality remains within the limits set by the user. For a range of PSNR values, the average Energy/image in PA reduces by 50%, where the reference is a static system without channel quality and image quality adaptation.

Modern wireless systems are increasingly incorporating adaptability to operate at low power under varying channel conditions and to increase yield under severe process variation. Effective adaptation requires built in tuning knobs in the RF front end circuits. Due to the sensitive nature of RF circuits traditional tuning knobs affect more than one specification simultaneously. To ensure optimal adaptation it is beneficial to have carefully designed tuning knobs that allows independent control of important specifications. In this paper the design of an inductorless RF LNA is discussed whose specifications can be traded off independently/ orthogonally of each other for reduced power consumption. Two built in tuning knobs are introduced for orthogonal adaptation of Gain and linearity. The proposed LNA, designed in 0.18μ CMOS achieves a 14 dB Gain and 30 dB OIP3 control range as its power consumption goes down by 20×.

In this research, a new post-manufacture tuning approach for yield improvement of advanced RF systems is developed. The proposed method first determines module level performances from the system level response (signature) to an applied RF diagnostic test using top-down model diagnosis. Then a constrained optimizer is used to determine the best module level tuning parameter values that satisfy system level specifications (bottom-up analysis) based on the determined performances of the individual modules in a power-conscious manner. Both top-down and bottom-up analysis techniques are supported by hierarchical RF behavioral models. The health (effects of process variations) of individual modules affects the relationship between module level tuning parameters and module level performance metrics and is factored into the tuning procedure. A key benefit of the proposed approach is that only a single test application is needed. Simulation results and hardware data prove the efficiency of the proposed tuning technique.

Low cost diagnosis of RF systems has become an important problem due to increased process variability effects on the performance of RF devices and the need to ramp-up RF IC yield rapidly. In the recent past, there has been work on diagnosing RF device model parameters from random “frequency-rich” test stimulus. In this paper, we develop a novel test stimulus generation approach which produces a compact, deterministic test stimulus in such a way that the RF DUT model parameters can be computed directly from the DUT response (called the DUT signature). This is achieved through use of a non-linear solver that adjusts the DUT model parameters iteratively until the model response to the applied test matches the observed DUT test response signature. It is shown that a small set of optimized tones in the frequency domain or an optimized transient waveform in the time domain can be used as test stimulus. It is shown how the use of embedded sensors in the RF design can expedite model parameter diagnosis. The practicality and accuracy of the proposed diagnosis approach is shown through simulations and hardware measurements.

In this paper, a novel built-in tuning technique to compensate for variability induced imperfections in RF subsystems is proposed. The test stimulus is obtained from a filtered digital pattern and the RF response is down-converted using an envelope detector. The resulting signal is mapped to a digital signature, such that the Hamming Distance between the observed and the golden signature represents the degree by which the circuit specifications (Gain, IIP3, EVM, etc) differ from the ideal. A hardware driven algorithm is used to minimize this Hamming Distance to concurrently optimize (tune) multiple RF specifications. As opposed to prior research, the method does not require the use of an on-chip digital signal processor and uses minimal on-chip hardware. Results obtained on a 2.4 GHz transmitter subsystem show significant impact of tuning on device specifications.

Testing of RF circuits for gain, nonlinearity and distortion specification generally requires the use of multiple test measurements and long test times contributing to increased test cost. Prior RF test methods have suffered from significant test calibration effort (training for supervised learners) when using compact tests or from increased test time due to direct specification measurement. In this paper, a novel RF test methodology is developed that: (a) allows RF devices to be tested for amplitude and phase distortion in test time comparable to what can be achieved using supervised learning techniques while retaining the accuracy of direct specification measurement, (b) allows multiple RF specifications to be determined concurrently from a single data acquisition and (c) does not require any training for accurate test specification computation. The proposed method based on amplitude modulated RF stimulus driven RF distortion extraction is shown to give excellent results across common RF performance metrics (RMS error <;1.4%) while providing ~10× improvements in test time compared to previous methods.

In this paper, a novel methodology for continuous real time monitoring of the performance metrics of RF front end modules is proposed. The presented technique involves determination of the RF system parameters using time domain parameter estimation techniques with minimal hardware overhead. The computation of the behavioral parameters of the RF modules is performed at periodic intervals using real time signals through the use of a "parallel model" of the RF front end in the baseband DSP. During specific intervals corresponding to high signal power levels, parameter estimation of the RF front end is performed using a model in the baseband as a reference. The presented technique is used for detection/tracking of performance degradation in analog/RF front ends in real-time and does not require the use of supervised learning algorithms as with prior performance monitoring techniques. Simulation results showing accurate tracking of the distortion parameters of an RF transmitter used to demonstrate the core ideas of this research.

With technology scaling, the impact of intra and inter-die process variations on the performance of mixed-signal/RF circuits has increased, making process monitoring a critical task in the overall silicon manufacturing flow. We propose a novel process-specification cause-effect monitoring scheme that allows the effects of process variations and shifts on device specifications to be monitored on a per-IC basis as opposed to existing techniques that rely only on electrical test data gathered across lots of wafers. The method relies on the use of alternate diagnostic tests under which the DUT response (alternate diagnostic signature) exhibits strong simultaneous correlation with its specifications as well as the critical process or circuit parameters with virtually zero extra test-time or test-hardware cost. Simulation results indicate that critical process parameters can be diagnosed accurately from the applied tests.

In this paper, a holistic yield recovery approach based on post manufacture tuning of RF circuits and systems under large as well as small multi-parameter process variations is developed. Marginally failing devices (small parameter deviations) are tuned using a nonlinear ¿Augmented Lagrange¿ algorithm driven optimization engine that includes test specification values and power consumption in its optimization framework. A novel built-in alternate tuning test is used to explicitly evaluate all the DUT specifications at each optimization iteration. For large parameter deviations well beyond the test specification limits of the DUT, determination of the different specification values is difficult. Such devices are tuned using a golden response tuning approach which optimizes the DUT specifications implicitly until the DUT is ¿good enough¿ to be tuned by the prior Augmented Lagrange algorithm. The proposed methodology enables yield recovery of devices not possible with earlier methods, avoids local minima and can be implemented at low cost.

In this paper, a fast RF BIST-driven post-manufacture tuning methodology for yield improvement of RF transceiver systems is presented. The core algorithms optimize multiple transceiver performance metrics concurrently using a hardware-iterated gradient search algorithm that uses diagnostic BIST data to guide the tuning of circuit and software level parameters. Intelligent ¿initial guess¿ values for the circuit and software tuning knobs at the start of the tuning process allow rapid convergence. Power consumption is given key consideration through the tuning process. Further, self-tuning is performed with little or no external tester support. The viability of the proposed scheme has been demonstrated through an experimental RF hardware prototype. Experimental results demonstrate significant yield recovery while allowing up to 10X savings in test/tuning time.

The recent demand in wireless standards capable of providing short-range, high-speed data transfer has accelerated the growth of the Ultra-Wide Band (UWB) standard. MB-OFDM (Multi Band Orthogonal Frequency Division Multiplexing) UWB devices suffer from frequency dependent non-idealities due to extreme wideband operation (3.1 to 10.6 GHz). Further these characteristics are subjected to process variations when implemented in nanometer technologies. In this paper we propose two BIST assisted methodologies for estimation and compensation of these effects. The proposed solutions differ in hardware vs. software tradeoffs. The improvement in the linearity of the mixer over a set of process instances and the tradeoffs involved are presented to validate the proposed methodology.

Design and test of high-speed mixed-signal/RF circuits and systems is undergoing a transformation due to the effects of process variations stemming from the use of scaled CMOS technologies that result in significant yield loss. To this effect, post-manufacture tuning for yield recovery is now a necessity for many high-speed electronic circuits and systems and is typically driven by iterative test-and-tune procedures. Such procedures create new challenges for manufacturing test and built-in self-test of advanced mixed-signal/RF systems. In this paper, key test challenges are discussed and promising solutions are presented in the hope that it will be possible to design, manufacture and test ¿truly self-healing¿ systems in the near future.

Voltage overscaling for power reduction in RF systems has been limited by the need to maintain sufficient overscaling guard bands to ensure that minimum signal quality requirements of the end to end communication link are met. In this paper, we propose error control mechanisms at the symbol (probabilistic symbol remapping) and bit levels (code based correction and feedback) that allow more aggressive voltage overscaling than is possible otherwise. Error control feedback is used to continuously monitor and control the tuning knobs of the front end RF circuitry to trade off signal quality vs. power consumption. Real time image and voice data is used to demonstrate this concept. Significant power savings is achieved using the proposed scheme while maintaining minimum signal quality as required by the wireless communication link.

Amplitude-to-amplitude (AM-AM) and amplitude-to-phase (AM-PM) distortion are two significant effects in power amplifiers at high output power levels. Traditional measurement of amplitude and phase distortion in RF power amplifiers requires the use of expensive vector network analyzers (VNAs). This paper proposes a low cost and accurate test methodology for AM-AM and AM-PM measurement using distortion-to-amplitude conversion using simple load board test circuitry along with the use of hardware and software based difference generation and peak detection mechanisms. It is seen that both distortion effects can be measured with high accuracy while allowing significant reduction in test cost.

In this paper, a process tunable, continuously adaptive wireless front end architecture and related adaptation algorithms are presented that allow an RF transceiver to function at minimum power irrespective of channel conditions and process variability induced performance loss in the RF front end and baseband interface. Current wireless transceiver front ends are designed for worst case channel conditions and a limited degree of post manufacture tuning is performed to compensate for process variations. It is shown how the proposed architecture can result in significant power savings over current practice without compromising system-level bit error rate. The adaptation methodology is applied to a WLAN transceiver design and hardware measurement data for an adaptive receiver is presented.

Design of a self compensating process variation tolerant RF low noise amplifier (LNA) is described. A novel non-intrusive mixing technique is proposed which enables minimal intrusion negative feedback in RF circuits making them process variation tolerant. The proposed design technique provides 18% yield improvement over comparable conventional LNA under severe process variation.

In this paper, a novel adaptive calibration technique for advanced RF front-ends is proposed in which sensors are implanted in the transmitter and the observed device test response to a special calibration test is compared against the known golden response to the same. Tuning 'knobs' which are built into the circuit are then used to minimize the error between the observed response and the golden response using an iterative tuning approach. In addition to circuit-level tuning, adaptive digital compensation techniques are employed in the baseband processor. It is shown that this results in increased transmit signal dynamic range over existing techniques and accurate loopback testing of the transceiver modules.

We propose a technique for low-cost testing of radio-frequency components integrating current signatures and alternate test methodology. The technique is suitable for non-invasive built-in test as well as low-cost automated test equipment (ATE) applications. Main features of the technique are (1) minimum loading on signal path by sampling supply current, (2) flexible test stimulus generation based on system constraints, (3) test time reduction by using a single test stimulus and data acquisition, and (4) accurate prediction of all specification values from the single excitation. Two experiments using the proposed implementation demonstrate the accuracy and efficiency of the technique on both single-balanced and double-balanced mixers built with two different technologies.

Modern wireless transceiver systems are often overdesigned to meet the requirements of low bit error rate values at high data rates under worst-case channel operating conditions (interference, noise, multi-path effects). This results in circuits being designed with ldquosufficientrdquo margins leading to lower efficiency and high power consumption. In this paper, we develop an adaptive power management strategy for RF systems that optimally trades-off power vs. performance for the RF front-end to maintain operation at or below a specified maximum bit error rate (BER) across temporally changing operating conditions. As the communication channel degrades, more power is consumed by the RF front end and vice versa. Since the maximum bit-error rate specification is not violated, minimum voice or video quality through the wireless channel is always guaranteed.