We present a distributed power supply and explore its load transient response and power side-channel security improvements. Typically, countermeasures against power side-channel attacks (PSCAs) are based on specialized dc/dc converters, resulting in large power and area overheads and they are difficult to scale. Moreover, due to limited output voltage range and load regulation, it is not feasible to directly distribute these converters in multicore applications. Targeting those issues, our proposed converter is designed to provide multiple fast-responding voltages and use shared circuits to mitigate PSCAs. The proposed three-output dc/dc converter can deliver 0.33–0.92 V with up to 1 A to each load. Comparing with state-of-the-art power management works, our converter has$2\times $load step response speed and$4\times $reference voltage tracking speed. Furthermore, the converter requires$9\times $less inductance and$3\times $less output capacitance. In terms of PSCA mitigation, this converter reduces the correlation between input power trace and encryption load current by$107\times $, which is$3\times $better than the best standalone work, and it only induces 1.7% area overhead and 2.5% power overhead. The proposed work also increases minimum traces to disclose (MTDs) by$1250\times $. Considering all the above, our work could be a great candidate to be employed in future multicore systems supplying varying voltages and resisting side-channel attacks. It is the first work bridging the gap between on-chip power management and side-channel security.

This paper presents a scalable single-input-multiple-output DC/DC converter targeting load transient response and security improvement for low-power System-on-Chips (SoCs). A two-stage modular architecture is introduced to enable scalability. The shared switched-capacitor pre-charging circuits are implemented to improve load transient response and decouple correlations between inputs and outputs. The demo version of the converter has three identical outputs, each supporting 0.3V to 0.9V with a maximum load current of 150mA. Based on post-layout simulation results in 32nm CMOS process, the converter output provides 19.3V/$\mu$s reference tracking speed and 27mA/ns workload transitions with negligible voltage droops or spikes. No cross regulation is observed at any outputs with a worst-case voltage ripple of 68mV. Peak efficiency reaches 85.5% for each output. With variable delays added externally, the input-output correlations can change 10 times and for steady-state operation, such correlation factors are always kept below 0.05. The converter is also scaled to support 6 outputs with only 0.56mm2more area and maintains same load transient response performance.

Existing power analysis techniques rely on strong adversary models with prior knowledge of the leakage or training data. We introduce side-channel analysis with unsupervised learning (SCAUL) that can recover the secret key without requiring prior knowledge or profiling (training). We employ an LSTM auto-encoder to extract features from power traces with high mutual information with the data-dependent samples of the measurements. We demonstrate that by replacing the raw measurements with the auto-encoder features in a classical DPA attack, the efficiency, in terms of required number of measurements for key recovery, improves by 10X. Further, we employ these features to identify a leakage model with sensitivity analysis and multi-layer perceptron (MLP) networks. SCAUL uses the auto-encoder features and the leakage model, obtained in an unsupervised approach, to find the correct key. On a lightweight implementation of AES on Artix-7 FPGA, we show that SCAUL is able to recover the correct key with 3,700 power measurements with random plaintexts, while a DPA attack requires at least 17,400 measurements. Using misaligned traces, with an uncertainty equal to 20 percent of the hardware clock cycle, SCAUL is able to recover the secret key with 12,300 measurements while the DPA attack fails to detect the key.

We propose a novel two-stage hybrid on-chip DC-DC converter targeting low power applications with multiple supply voltage domains and dynamic workloads. The converter has a nominal input voltage of 1.2V and generates two asymmetrically regulated output voltages simultaneously. The high-power output channel provides voltages ranging from 0.3V to 1.1V and up to 12mA load current; on the other hand, the low power output channel delivers voltages varying from 0.3V to 0.5V with up to 1mA load current. The high-power output is able to respond to load transition requests with a peak voltage slew rate of 16V/µs and maximum voltage ripple of 49mV. During load transitions at the high-power channel, the low-power output voltage with fixed load remains stable with less than 7.6% ripples and a worst case droop of 45 mV. In addition, when load transitions are requested at both output channels simultaneously, there are no observable voltage droops/spikes at the outputs; thus, cross regulations are significantly reduced. Even with input voltage glitches, additional voltage spikes/droops at each output are less than 5%. Peak power efficiency achieved is 73%.

Approximate Computing is an emerging computing paradigm where one exploits inherent error resilience of certain applications (e.g., digital signal processing, multimedia and artificial intelligence) and trades off absolute computation precisions for performance, power, area, and/or efficiency gains. Approximate memory is a sub-branch of general approximate computing focusing on memory systems that trade off perfect data fidelity for increased storage density and reduced energy consumption for both memory and IO. This paper presents a new way to achieve approximate memory for natural sampled data (sound, sensor data, image and video frames) by applying the well known discrete cosine transformation (DCT) in one dimension between the last level cache and main memory to reduce memory traffic while maintaining acceptable quality degradations. By using state-of-the-art approximate DCT transformations, the proposed scheme achieves 20.3% of storage area at 37dB PSNR and SSIM = 0.99. If further quality degradation up to SSIM ≈ 0.9 is allowed, the storage saving can be up to 40%. The critical path of the circuit is comparable to state of the art approximate memory schemes, with only 3 levels of 8-bit adders (14 adders per 8-byte data block).

With the advancement and miniaturization of transistor technology, hundreds of cores can be integrated on a single chip. Network-on-Chips (NoCs) are the de facto on-chip communication fabrics for multi/many core systems because of their benefits over the traditional bus in terms of scalability, parallelism, and power efficiency. However, relative power consumption of NoC has been increasing with the increase in the number of cores on a chip, as communication costs much more time and energy than that of computation. Approximating computing concept can be applied in the NoC to reduce power consumption by approximating the communication data of emerging data-intensive applications, such as machine learning and big data analytics, that can tolerate errors. In this paper, we present an architecture for NoC approximation, and also provide preliminary results (which shows significant improvement) to support the importance of approximate communication solution for energy-efficient and high-performance NoC. Then we present various approximate communication solutions for reducing data movement in NoC. Finally, we discuss about the challenges and software and hardware overheads to adapt approximate technique in NoC, and also provide tentative solutions to address those challenges.

As compute capabilities continue to scale, memory capacity and bandwidth continue to lag behind. Data compression is an effective approach to improving memory capacity and bandwidth; but prior works have focused primarily on lossless compression and retrieval for data-critical applications. While data integrity is critical to many applications, a growing number of memory-bound applications contain non-critical program data; this property can be exploited to improve memory performance and capacity. In this work, we enable approximate storage to exploit the inherent error resilience of multimedia and other applications, through lossy compression, to improve storage without adversely affecting application functionality. We realize an incidence of approximate storage through modification of the Base-Delta-Immediate algorithm to create a lossy memory compression algorithm. We conclude that approximate storage is an effective and promising technique for improving effective memory capacity and decreasing the energy cost of memory access; results show that memory capacity can be increased by 15% with only 3% loss in image recognition application quality.

With the advancement and miniaturization of transistor technology, hundreds of cores can be integrated on a single chip. Network-on-Chips (NoCs) are the de facto on-chip communication fabrics for multi/many core systems because of their benefits over the traditional bus in terms of scalability, parallelism, and power efficiency [20]. Because of these properties of NoC, communication architecture for different layers of a deep neural network can be developed using NoC. However, traditional NoC architectures and strategies may not be suitable for running deep neural networks because of the different types of communication patterns (e.g. one-to-many and many-to-one communication between layers and zero communication within a single layer) in neural networks. Furthermore, because of the different communication patterns, computations of the different layers of a neural network need to be mapped in a way that reduces communication bottleneck in NoC. Therefore, we explore different NoC architectures and mapping solutions for deep neural networks, and then propose an efficient concentrated mesh NoC architecture and a load-balanced mapping solution (including mathematical model) for accelerating deep neural networks. We also present preliminary results to show the effectiveness of our proposed approaches to accelerate deep neural networks while achieving energy-efficient and high-performance NoC.

Microring resonators, one of the key components in nanophotonic networks-on-chip (NoCs), are highly sensitive to process and temperature variations. The consequential resonant wavelength deviations negatively impact reliable on-chip communication. To revert resonant wavelengths to their desired values and recover bandwidth, power trimming is usually applied; unfortunately, this technique incurs considerable energy overhead. In this work, we present an energy-efficient power trimming technique that considers the group shifting effect caused by temperature variations. Experimental results show that our approach improves energy-efficiency by up to 30% (with negligible ~ 3% bandwidth degradation), over the next best power trimming method.

Whereas buffers significantly impact Network-on-Chip (NoC) performance, they also account for up to 75% and nearly 50% of NoC router area and power respectively. Traditionally, SRAM has been used as an area and power efficient implementation of the router buffer. However, motivated by the smaller size and lower-power potential of planar embedded DRAM (eDRAM), we implement the router buffer using a 3T NMOS eDRAM for improved power and area efficiency. We demonstrate that the lifetime of flits stalled in the NoC router buffer is much shorter than the retention time of currently available eDRAM. This observation allows us to make the appropriate trade-off in size and sense-amplifier complexity to meet requirements of power and performance. A low-overhead need-based refresh mechanism is further explored. With a conservative buffer design using 65nm CMOS technology, our method reduces buffer area by up to 52% and power by 43%, while maintaining performance similar to a SRAM-based buffer. In a NoC router with 128-bit channel width, we achieve 26% and 11% reduction of total router area and power respectively. We conclude that eDRAM-based buffer is a power and area efficient alternative to SRAM-based buffer for NoC router design.

Balancing cache energy efficiency and reliability is a major challenge for future multicore system design. Supply voltage reduction is an effective tool to minimize cache energy consumption, usually at the expense of increased number of errors. To achieve substantial energy reduction without degrading reliability, we propose an adaptive fault-tolerant cache architecture, which provides appropriate error control for each cache line based on the number of faulty cells detected at reduced supply voltages. Our experiments show that the proposed approach can improve energy efficiency by more than 25% and energy-execution time product by over 10%, while improving reliability up to 4X using Mean-Error-To-Failure (METF) metric, compared to the next-best solution at the cost of 0.08% storage overhead.

We exploit the inherent information redundancy in the control path of Network-on-Chip (NoC) routers to manage transient errors, preventing packet loss and misrouting. Outputs of the routing arbitration units in NoC routers can be used to determine arbitration failures, because the valid arbitration outputs are a subset of all possible values. This feature is exploited to detect and correct logic and register errors in the router arbitration control path. The proposed method is complementary to other error management methods for NoC routers. An analytical reliability model of our method is provided, including parameters such as logic unit size, different error rates for logic gates and registers, and the location of faulty elements. Compared to triple-modular redundancy (TMR), the proposed method improves the arbiter reliability by two orders of magnitude while reducing the total area and power by 43% and 64%, respectively. In the presented case studies, two traffic traces from the PARSEC benchmark suite are used to evaluate the average latency and energy consumption. Simulations performed on a 4× 4 NoC show that our method reduces the average latency by up to 50% and reduces average energy by up to 70% compared to other methods.

We propose a concatenate error detection method that exploits inherent information redundancy in network-on-chip (NoC) router, to address transient route computation errors. In our previous works, inherent information redundancy has been successfully employed to management transient errors in routers using XY deterministic routing algorithm. To prevent misrouting caused by transient errors injected in the partially adaptive router, we improve our previous method by using concatenate error detection logic. The proposed method is applied to a recent partially adaptive router based on logic-based distributed routing (LBDR). Analysis and simulation results show that the proposed method reduces the residual error rate by up to 1.98× and 3.47× over our previous approach and triple modular redundancy (TMR), respectively. More importantly, the proposed method consumes 2.6× less area and 2.1× less power consumption compared to TMR.

We propose a series of fine-grained splitting transmission methods to address permanent errors in Network-on-Chip (NoC) links, maintaining high throughput and ensuring reliability. While prior permanent error management approaches discard the entire or half link, our proposed methods greatly improve wire utilization in the presence of permanent errors. A case study shows that our methods achieve throughput improvement of 234% and 56%, respectively, compared to fault-tolerant routing and half-splitting methods in the presence of high number of permanent errors.

High-end MPSoC systems with built-in high-radix topologies achieve good performance because of the improved connectivity and the reduced network diameter. In high-end MPSoC systems, fault tolerance support is becoming a compulsory feature. In this work, we propose a combined method to address permanent and transient link and router failures in those systems. The LBDRhr mechanism is proposed to tolerate permanent link failures in some popular high-radix topologies. The increased router complexity may lead to more transient router errors than routers using simple XY routing algorithm. We exploit the inherent information redundancy (IIR) in LBDRhr logic to manage transient errors in the network routers. Thorough analyses are provided to discover the appropriate internal nodes and the forbidden signal patterns for transient error detection. Simulation results show that LBDRhr logic can tolerate all of the permanent failure combinations of long-range links and 80% of links failures at short-range links. Case studies show that the error detection method based on the new IIR extraction method reduces the power consumption and the residual error rate by 33% and up to two orders of magnitude, respectively, compared to triple modular redundancy. The impact of network topologies on the efficiency of the detection mechanism has been examined in this work, as well.

In this work, we present a new error control method to improve the energy efficiency and reliability of network-on-chip (NoC) links. The proposed method combines the error control coding (ECC) capabilities of the NoC's datalink and network layers to dynamically adjust the error control strength in variable noise conditions. Network-layer ECC is used in low noise conditions and error control strength is enhanced by adding datalink-layer ECC in high noise regions. To switch between the two ECC modes at runtime without interrupting normal operation, we propose a dual-layer cooperative error control protocol and its hardware-efficient implementation using the concept of product codes. Theoretical analyses of residual error rate and performance show the proposed method outperforms previous single-layer fixed and adaptive error control schemes. Compared to previous solutions, the proposed method reduces residual packet error rate by up to four orders of magnitude, achieves up to 72% energy reduction and improves average latency by up to 64%. The energy and latency reduction benefits are maintained as the routing path length and packet size increase, at the cost of a moderate increase in area overhead.

We exploit the inherent information redundancy in the control path of Networks-on-Chip (NoCs) routers to manage transient errors, preventing packet loss and misrouting. Unlike fault-tolerant routing, our method does not drop packets when faults occur in routers and thus does not increase the burden on neighboring routers. Unlike the NoC interconnect links, the routing operation is nonlinear and standard error control coding methods cannot be used. Instead, our method exploits existing information redundancy in the router, significantly reducing the area overhead and power consumption compared to triple-modular redundancy (TMR). An analytical reliability model of our method is provided, including parameters such as circuit size, different error rates for logic gates and registers, and the location of a faulty element. Compared to TMR, the proposed method improves the arbiter reliability by two orders of magnitude while reducing the total power and area by 43% and 64%, respectively. Simulations performed on a 4x4 NoC show that our method reduces the average latency by up to 90% and 12% over no-protection and TMR methods, respectively.

Error control is imperative for reliable Networks-on-Chip (NoCs) design. In this demo session, we will present a CAD tool---a flexible and parallel NoC simulator. Our simulator evaluates the impact of different error control mechanisms on NoC performance and energy consumption in various noise and traffic injection scenarios. Our message passing interface language-based simulator can be executed on multiprocessors or server clusters. Multiple built-in blocks provide flexibility to evaluate different error control methods.

To improve noise tolerance of link transmission and router buffers, we propose an error control scheme that integrates a powerful link error recovery method, an efficient buffer error correction coding, and an algorithm to further manage the loss of header and tail flits in a packet. With this method, header and tail flits can be effectively protected, reducing network saturation. Simulation results show the proposed scheme achieves up to a 9x improvement in operation time before saturation and 26% higher throughput than other error control methods. Simulations performed on a parallel FFT application mapped on a 4×4 mesh NoC demonstrate that the proposed error control scheme reduces the total computation time over a previous method in the high noise region.

This paper presents a new technique that takes advantage of the differing temperature dependences in low-voltage interconnect links and higher voltage transceivers. The link and transceiver are dynamically retimed as the system temperature changes. This delay borrowing enables the link to maintain a frequency requirement despite temperature-induced frequency variations in excess of 200%, and enables the link to operate at lower voltages than possible with a non-temperature aware link. In addition to improved tolerance of environmental variations, the proposed approach achieves energy savings of up to 40% in a commercial 65 nm technology, including the energy overhead of the temperature-aware system. Further, the delay borrowing system is shown to decrease temperature-induced delay variations by 85%.

We propose a transient and permanent error co-management method for NoC links to achieve low latency, high throughput and high reliability, while maintaining energy efficiency. To reduce the energy overhead, a configurable error control coding adapts the number of redundant wires to the varying noise conditions, achieving different error detection capability. Infrequently used redundant wires are used as spare wires to replace broken links. Furthermore, a packet rebuilding/restoring algorithm that cooperates with a shortened error control coding method is proposed to support a low-latency splitting transmission. With this co-management method, we manage transient errors and a small number of permanent errors, without using extra spare wires, to reduce the need for adaptive routing. Simulation results show that the proposed method achieves up to 71% packet latency reduction and 20% throughput improvement, compared to previous methods. Case studies show that our method reduces the energy per packet by up to 68% and 48% for low and high permanent error conditions, respectively.

This paper presents a flexible parallel simulator to evaluate the impact of different error control methods on the performance and energy consumption of networks-on-chip (NoCs). Various error control schemes can be inserted into the simulator in a plug-and-play manner for evaluation. Moreover, a highly tunable fault injection feature is developed for modeling various fault injection scenarios, including different fault injection rates, fault types, fault injection locations, and faulty flit types. Case studies performed in the proposed flexible simulation environment are presented to demonstrate the impact of a set of error control schemes on NoC performance and energy in different noise scenarios. This paper also uses the simulator to provide design guidelines for NoCs with error control capabilities.

We present a self-contained adaptive system for detecting and bypassing permanent errors in on-chip interconnects. The proposed system reroutes data on erroneous links to a set of spare wires without interrupting the data flow. To detect permanent errors at runtime, a novel in-line test (ILT) method using spare wires and a test pattern generator is proposed. In addition, an improved syndrome storing-based detection (SSD) method is presented and compared to the ILT method. Each detection method (ILT and SSD) is integrated individually into the noninterrupting adaptive system, and a case study is performed to compare them with Hamming and Bose-Chaudhuri-Hocquenghem (BCH) code implementations. In the presence of permanent errors, the probability of correct transmission in the proposed systems is improved by up to 140% over the standalone Hamming code. Furthermore, our methods achieve up to 38% area, 64% energy, and 61% latency improvements over the BCH implementation at comparable error performance.

This paper presents a brief survey of the state of the art in nanoscale electronics, with special emphasis on room-temperature nanoscale ballistic deflection transistors (BDTs) and T-branch junctions (TBJs). Both devices are planar structures etched into a two-dimensional electron gas (2DEG). Extremely low capacitances (~0.2 fF) in the 2DEG system and low switching voltages (~0.15 V) predict THz performance and ultra-low power consumption, making BDTs and TBJs among the most promising and versatile of ballistic nanoelectronic devices. Obstacles in circuit and logic design using the BDT are presented along with potential solutions. I-V characteristics from a fabricated BDT and simulation results from a two-input BDT NAND gate are provided. Future plans to facilitate large-scale integration are discussed.

This paper presents a novel adaptive voltage scheme based on a lookahead circuit that checks the transmitter buffer for data transitions. The advanced knowledge of incoming data patterns is used to adjust the link swing voltage, improving delay and energy performance. In the presented example system, a transition detection circuit is used to check the transmitter buffer for rising transitions (dasia0psila in cycle t, dasia1psila in cycle t+1). When a rising transition is detected, a higher supply voltage is applied to the driver for a small portion of the clock cycle to boost the rising edge delay, improving link performance. A lower voltage is used for all other transmissions, improving the delay performance of falling edge transitions and the link energy dissipation. For a 1 GHz link frequency, the proposed approach improves energy dissipation by 45% compared to a traditional two-inverter buffer. An energy savings of up to 15% is achieved compared to a previously proposed dual-voltage scheme.

A multipurpose simulator for ballistic nanostructures, based on classical mechanics of electrons at the Fermi level, has been successfully implemented. Despite the simplicity of the model, the simulator successfully reproduces a number of experimental results, and is shown to consistently match observed current-voltage characteristics and magnetoresistance phenomena. The simulator results provide design guidelines for devices which operate on ballistic transport principles. Using the simulator, preliminary logic structures have been designed based on the ballistic deflection transistor.

We present an adaptive error control scheme that employs a link quality grading technique and a burst error prediction mechanism, in order to handle multi-wire and multi-cycle errors, respectively. Our approach enables the transmitter to select the most effective error-control scheme for the particular link quality. Using this method, we can improve switch-to-switch throughput by 4X and reduce power consumption by 70%, compared to retransmission-only and retransmission-plus-fixed-coding approaches.

The wide use of voltage scaling along with pipelining makes flip-flops particularly important at ultra-low voltages. In this paper, the impact of voltage scaling on the performance of flip-flops is analyzed. Four representative flip-flops are compared at ultra-low voltages, for delay, energy and energy-delay-product (EDP). With decreasing supply voltage, a pulse-triggered flip-flop and a sense-amplifier based flip-flop produce smaller increase in setup time, compared with a master-slaver flip-flop. For energy efficient operation at ultra-low voltages, a transmission-gate based master-slave flip-flop achieves the smallest EDP at low switching activities, while a pulse-triggered flip-flop becomes more energy efficient at high switching activities.

In nanoscale system design, increased susceptibility to variation makes robustness an important concern, along with speed and power. To consider robustness amidst variations, fixed performance parameters can be replaced with their distributions during the design process. In this paper, supply voltage selection is used to manage the trade-offs among speed, power, and temperature robustness. Optimal supply voltages are found for different performance goals by considering the variance of the design as well as the mean performance. Furthermore, overall design margins can be increased by finding the best combinations of means and variances in each design decision.

Energy-delay product (EDP) minimization in nanoscale domino logic circuits by supply voltage selection and device sizing is presented. It is shown that the dependence of leakage current on transistor width introduces an additional factor in sizing for leakage dominant circuit blocks. A model is presented for EDP-optimal sizing of the evaluation tree of domino AND-type gates, and the effects of sizing the static output inverter and keeper on EDP are discussed. The model is applied to an 8x8 carry-save multiplier, which achieves 10% reduction in EDP at low frequencies compared to minimum width sizing.

Aggressively scaled supply voltage has been touted as one of the most powerful mechanisms for improving reliability and reducing power consumption in nanometer technologies. Sophisticated adaptive power management techniques vary supply voltage from nominal to ultra-low values to implement adaptive VLSI systems that gracefully respond to varying workload demands for improved energy efficiency. Unfortunately, ultra-low voltage (sub-volt for current technologies) operation has been constrained by performance limitations. In this paper, the current state of low-voltage VLSI design is evaluated; techniques for maintaining acceptable throughputs at ultra-low voltages are reviewed; and trends and prospects for ultra-low voltage VLSI systems are presented

Body biasing, inverter topology, and charge restoring techniques for subthreshold domino circuits are evaluated for speed, energy, and noise immunity. Forward body-biasing minimizes energy, whereas dynamic body-biasing, effective in minimizing leakage, exacerbates clock feedthrough. At low frequencies, the traditional "keeper" scheme is energy efficient and solves problems related to leakage and charge-sharing. Pre-charging internal nodes minimizes charge-sharing but increases delay and power, particularly for large fan-in gates. For these gates at moderate frequencies, the two methods together strike a judicious balance among power, delay, and robustness