Recent static timing analysis (STA) tools have utilized task dependency graph (TDG) parallelism to enhance the STA runtime performance. Although TDG parallelism shows promising speedup, the overhead of scheduling a TDG can become dominant as the TDG becomes larger. To minimize the scheduling overhead, several TDG partitioning algorithms have been proposed to reduce the TDG size without affecting its task parallelism. Despite improved performance, existing TDG partitioners all fall short of incremental partitioning, limiting their practical use in STA tools that support timing-driven operations. To overcome this limitation, we propose iTAP, an incremental TDG partitioner to fully leverage the power of TDG partitioning in task-parallel STA applications. Compared to a state-of-the-art full TDG partitioner, iTAP enhances the overall STA performance by up to 2.97×.

Quantum circuit simulation (QCS) plays an important role in the designs and analysis of a quantum algorithm, as it assists researchers in understanding how quantum operations work without accessing expensive quantum computers. Despite many QCS methods, they are largely limited to simulating one input at a time. However, many simulation-driven quantum computing applications, such as testing and verification, require simulating multiple inputs to reason a quantum algorithm under different scenarios. We refer to this type of QCS as batch quantum circuit simulation (BQCS). In this paper, we present BQSim, a GPU-accelerated batch quantum circuit simulator. BQSim is inspired by the state-of-the-art decision diagram (DD) that can compactly represent quantum gate matrices, but overcomes its limitation of CPU-centric simulation. Specifically, BQSim uses DD to optimize a quantum circuit for reduced BQCS computation and converts DD to a GPU-efficient data structure. Additionally, BQSim employs a task graph-based execution strategy to minimize repetitive kernel call overhead and efficiently overlap kernel execution with data movement. Compared with three state-of-the-art quantum circuit simulators, cuQuantum, Qiskit Aer, and FlatDD, BQSim is 3.25×, 159.06×, and 311.42× faster on average.

Statistical Static Timing Analysis (SSTA) is a crucial technique in digital circuit design because it addresses on-chip variations (OCV) by propagating timing distributions instead of fixed delays. However, the computational complexity of SSTA demands significant memory and long runtimes. While GPUs offer opportunities to accelerate SSTA, their limited memory capacity makes it challenging to handle large-scale SSTA workloads. To address this challenge, we propose a statistical timing graph (STG) scheduling algorithm combined with a GPU memory management strategy. We have shown up to $4.9 \times$ speedup on a GPU with 16 GB memory compared to a 20-thread CPU baseline when solving an 18.2 GB STG.

Recent static timing analysis (STA) engines have leveraged task dependency graph (TDG) parallelism to accelerate various STA algorithms, including graph-based analysis and path-based analysis. Despite the promising speedup via task parallelism, the scheduling cost of a TDG has become dominant when handling large TDGs. To overcome this challenge, we propose G-PASTA, a simple and fast TDG partitioning algorithm to reduce the scheduling cost of large task-parallel STA algorithms. By harnessing the power of GPU computing, G-PASTA incurs minimal cost of partitioning while bringing significant runtime improvement to task-parallel STA algorithms. Compared to a state-of-the-art CPU-based TDG partitioner, G-PASTA is up to 41.8× faster in partitioning runtime and can improve the overall STA performance by 43% on large designs.

Graph partitioning is essential for understanding the structure of a dataset, such as social networks and web pages. Among various graph partitioners, stochastic block partitioning (SBP) has shown promise in handling complex graphs with varying community sizes or strong intra-community connections. However, the sequential nature of the Monte Carlo Markov Chain iterations and the stochastic proposal generation process limit the efficiency and scalability of SBP. To overcome this limitation, this paper introduces GSAP, a GPU-accelerated stochastic graph partitioner, to enhance the runtime performance of SBP. We propose a parallel algorithm to speed up the generation process of stochastic proposals on GPU. Additionally, we accelerate the calculation of the minimal description length by dividing the formulation into several independent computations. To achieve better performance, we introduce an efficient blockmodel update algorithm to dynamically manage the blockmodel matrix on GPU. Our experimental results on the 2022 HPEC GraphChallenge dataset demonstrate that GSAP can achieve up to 12.3 × and 60.9 × runtime speedup on a single A4000 GPU compared to two CPU-parallel state-of-the-art SBP algorithms.

In this study, robust biological filters with an external control to match a desired input/output (I/O) filtering response are engineered based on the well-characterized promoter-RBS libraries and a cascade gene circuit topology. In the field of synthetic biology, the biological filter system serves as a powerful detector or sensor to sense different molecular signals and produces a specific output response only if the concentration of the input molecular signal is higher or lower than a specified threshold. The proposed systematic design method of robust biological filters is summarized into three steps. Firstly, several well-characterized promoter-RBS libraries are established for biological filter design by identifying and collecting the quantitative and qualitative characteristics of their promoter-RBS components via nonlinear parameter estimation method. Then, the topology of synthetic biological filter is decomposed into three cascade gene regulatory modules, and an appropriate promoter-RBS library is selected for each module to achieve the desired I/O specification of a biological filter. Finally, based on the proposed systematic method, a robust externally tunable biological filter is engineered by searching the promoter-RBS component libraries and a control inducer concentration library to achieve the optimal reference match for the specified I/O filtering response.

This paper describes our strategy to operate WSN with or without security based on our measurements of energy consumption using CrossBow and Ember sensor nodes. It was found that the node microcontroller's CPU operates for substantially longer times for both hashing and encryption operations compared to the time for handling messages without any security. However, the associated overall increased energy consumption is relatively insignificant. The longer high-power radio transmission times due to hashing were more costly. We provide design guidelines to apply security for energy limited WSN.

Both correct transmission using hashing and protection of messages using encryption in sensor nodes require additional energy. This paper describes our measurement results for energy consumption in CrossBow and Ember sensor nodes for the process of exchanging data messages between nodes both in the clear and in a protected form. Full strength algorithms were loaded into and executed in nodes. It was found that the CPU operates for substantially longer times for both hashing and encryption operations compared to the time for handling messages without any security. The longer radio transmission times due to hashing were especially costly. Hence, security algorithms have great impacts on energy consumption in sensor nodes. For the full operational mode, with CPU processing and also radio transmission of messages, our results indicate that the lifetime of a transmitting node in a security regime is only about one-half of the lifetime without security.

This paper describes the design, prototype implementation and deployment of a key management protocol for sensor networks. In order to exchange protected messages between sensor nodes in a wireless sensor network, secret shared cryptographic keys must be established between the nodes of the network. Several key management schemes have been proposed in the literature, but these schemes are not suitable for real-life deployment. In this paper, we approach the problems of key management protocol differently from other reported results. We first analyzed functionality, feasibility and flexibility of the current key management protocols. Then, we introduce the concept of the Trusted Base Station as the foundation of our new protocol. The results of our implementation and deployment in a real WSN environment show that our theoretical results and claims are supported by the results of practical tests and measurements of operational efficiency.

WSN nodes are usually powered by batteries. Energy consumption during node operation determines battery life. Power consumption depends on the different hardware and software components in a WSN node and their various activities. In order to determine the life of the battery, we must measure the energy consumption of a node that is active in a network. That is, we must know the power consumption and time duration for node activities including computations, and RF transmission and reception. In this paper, we introduce an easy and accurate method for dynamic energy measurements without disturbing the node or network. The method consists of an oscilloscope, which can stream digitized voltages into a PC, which calculates the profile of energy consumption. We employed this capability to determine energy consumption for different security algorithms in CrossBow MICA2 nodes.