Electroencephalogram (EEG) signal processing is essential for achieving accurate and efficient real-time edge computing, particularly in resource-constrained smart wearables. They demand lightweight and optimized solutions for rapid analysis and decision-making. However, the higher dimensionality of EEG signals introduces challenges of latency and computational cost on edge devices. This article presents E-OptEEG, a hybrid ensemble metaheuristic framework designed to bring edge-optimized EEG processing and feature selection specifically for low-powered devices. The E-OptEEG framework integrates the strengths of multiple evolutionary feature selection algorithms, leveraging an ensemble threshold voting scheme to combine their outputs and identify the most relevant features. Further, E-OptEEG employs a fruit-fly optimization algorithm with deep metric feature transformation based on cosine similarity to transform the refined feature set to a minimal latent space. E-OptEEG demonstrates its ability to identify and select the most relevant features, enabling effective emotion and sentiment analysis from EEG signals captured through edge-powered wearable devices. Experimental evaluations against state-of-the-art feature selection techniques on three different EEG-based behavior modeling datasets highlight the framework’s effectiveness, achieving an average accuracy exceeding 98% with an average accuracy improvement of 2.55%. The E-OptEEG framework exemplifies the potential for lightweight artificial intelligence solutions to enable real-time, resource-efficient decision-making in wearable electronics.

As Deep Neural Network (DNN) models became more complex, the escalating computational demands on hardware made DNN accelerators a critical research topic. The rapid growth of DNN models required DNN accelerators to keep pace with these computational demands. However, the cost of hardware design was significant, and hardware and software were tightly coupled in the design of DNN accelerators. Much research on HW/SW co-design was evident, highlighting the importance of having a comprehensive framework to help find the optimal hardware and software design during the design phase. The cost models used in most of the current research relied on data reuse and mathematical estimation to calculate costs, an approach that was fast but inaccurate. In this article, we propose a framework for HW/SW co-design and introduce a hybrid cost model based on Gem5 that provides fast and precise performance evaluation. The framework uses a memory-centric approach to accurately model off-chip memory behavior. In addition, we discuss how to find the best design in a large co-design space and integrate a design point through a traffic generator and a cost model. Finally, we demonstrate that our framework can accurately assist DNN accelerator developers in exploring the optimal hardware and software co-design quickly and efficiently.

Reducing energy consumption for data transmissions and prolonging network lifetime are crucial in the design of energy‐efficient routing protocols. The proportion of successful data transmissions is significant for the reduction of data transmission and traffic load energy consumption, although the energy remaining in node is important for prolonging network lifetime. In this study, the authors propose an energy‐efficient cross‐layer design for the network layer and medium access control (MAC) layer that reduces energy consumption and prolongs network lifetime. In the network layer, a minimum transmission energy consumption (MTEC) routing protocol is proposed for selecting the MTEC path for data transmission, based on the proportion of successful data transmissions, the number of channel events, the remaining node energy of nodes and the traffic load of nodes. The authors design an adaptive contention window (ACW) for the MAC layer that provides nodes with high successful transmission rates with greater opportunity for contending for a channel to save energy. They used simulations to compare the proposed cross‐layer design (MTEC with ACW) with related protocols, including dynamic source routing, traffic‐size aware and the Varaprasad routing protocol. The simulation results showed that the proposed cross‐layer design (MTEC with ACW) provided better packet delivery rate and throughput than existing protocols. MTEC with ACW also exhibited lower‐energy consumption during data transmission and a higher network lifetime than existing protocols.

Power gating is an effective technique for reducing leakage power in deep submicron CMOS technology. Microarchitectural techniques for power gating of functional units have been developed by detecting suitable idle regions and turning them off to reduce leakage energy consumption; however, wakeup of functional units is needed when instructions are ready for execution such that wakeup overhead is naturally incurred. This study presents time-based power gating with reference pre-wakeup (PGRP), a novel predictive strategy that detects suitable idle periods for power gating and then enables pre-wakeup of needed functional units for avoiding wakeup overhead. The key insight is that most wakeups are repeated due to program locality. Thus, the pre-wakeup predictor learns the wakeup events and selects which prior branch instruction can provide early wakeup (wakeup patterns are visible); these information are then used to adequately prepare available functional units for instruction execution. Simulation results with benchmarks from SPEC2000 applications show that substantial leakage energy reduction with negligible performance degradation (0.38% on average) is worthwhile.

As the number of cores on a chip increases, power consumed by the communication structures takes a significant portion of the overall power budget. In this article, we first propose a circuit-switched interconnection architecture which uses crossroad switches to construct dedicated channels dynamically between any pairs of cores for nonhuge application-specific SoCs. The structure of the crossroad switch is simple, which can be regarded as a NoC-lite router, and we can easily construct a low-power on-chip network with these switches by a system-level design methodology. We also present the design methodology to tailor the proposed interconnection architecture to low-power structures by two proposed optimization schemes with profiled communication characteristics. The first scheme is power-aware topology construction, which can build low-power application-specific interconnection topologies. To further reduce the power consumption, we propose the second optimization scheme to predetermine the operating mode of dual-mode switches in the NoC at runtime. We evaluate several interconnection techniques, and the results show that the proposed architecture is more low-power and high-performance than others under some constraints and scale boundaries. We take multimedia applications as case studies, and experimental results show the power savings of power-aware topology approximate to 49% of the interconnection architecture. The power consumption can be further reduced approximately 25% by applying partially dedicated path mechanism.

In this study, an indoor localization based on the received signal strength indication (RSSI) in wireless sensor networks (WSN) is proposed. The presented approach proceeds in two phases: the first phase is based on the recorded received signal strength at the certain location. The interpolation, curve fitting and an adaptive neural fuzzy inference system (ANFIS) are used to develop the indoor propagation model, respectively. Thus the strength of the received radio signal can be converted to a physical distance approximately; in the second phase, based on the available distances from the positions localized in the test bed are estimated by using an extended Kalman filter (EKF). In comparison among the propagation models based on the interpolation, ANFIS and curve fitting, the experimental results show that the proposed approach provides a precise performance.

NOC architectures have to deliver good latency-throughput performance in the face of very tight power and area budgets. However, the latency and the power consumption for transferring information down the transmitter stack, through the channel, and up the receiver stack might be unacceptably high. In this paper, we evaluate the designs of packet-switched and the proposed circuit-switched NOCs in detail, and we advocate using circuit-switched NOC as it is more attractive for application-specific SOC designs because of communication localization. We implement and synthesize the designs of packet-switched and circuit-switched NOCs, and we take multimedia applications as our case studies. The experimental results show that the area, latency and the energy consumption of packet-switched NOC are much larger than that of circuit-switched NOC.

As the number of cores on a chip increases, power consumed by the communication structures takes significant portion of the overall power-budget. We first propose a novel 2D segmented interconnect architecture, which uses crossroad switches to dynamically construct a dedicated communication path between any two cores. We then present two application-specific bus operation schemes (normal mode and lease line mode). Each switch may operate with a "lease line", which can dynamically offer a dedicated path between two highly-communicative cores for a specific period according to the application characteristics. Finally, we present a concept of wrappers to help designers use our crossroad architecture as communication backbone. We take the JPEG and MPEG4 reference codes as our case studies and experimental results show the power consumptions can be saved if we dynamically control NoC switches when the behavior of the embedded software is well-known.

To support various bandwidth requirements for mobile multimedia services for future heterogeneous mobile environments, a transcoding video proxy is usually necessary to provide adapting video streams to mobile clients by not only transcoding videos to meet different needs on demand, but also caching them for later use. Traditional proxy technology is not applicable to a video proxy because it is less cost-effective to cache the complete videos to fit all kind of clients in the proxy server. In this paper, we propose the object relation graph (ORG) to manage the static relationships between video versions, and utilize the cached object relation tree (CORT) and replacement algorithm to manage video segments cached in the proxy dynamically. Experimental results show that the proposed algorithm significantly outperforms companion schemes in terms of the byte hit ratios.

As the number of cores on a chip increases, power consumed by the communication structures takes significant portion of the overall power-budget. The individual components of the SoCs will be heterogeneous in nature with widely varying functionality and communication requirements. The communication topology should possibly match communication workflows among these components. In this paper, the authors first proposed an interconnection architecture for SoC, which uses crossroad switches to construct a dedicated communication path dynamically between any two cores. Then a design methodology for constructing network on chip (NoC) was presented for application-specific computer systems with profiled communication characteristics. A core placement tool, which automatically maps cores to a communication topology such that the total communication energy can be minimized, was proposed. Experimental results show that the design methodology can generate optimized on-chip networks with fewer resources than meshes and tori, and the power saving approximates to 40%.