The authors examine the issue of how packet delivery can be made more reliable over ATM networks. While forward error correction (FEC) techniques have been proposed in the past by many researchers to address the data loss issues in ATM networks, the focus of the paper is on analyzing the cost-performance aspects of cell-level FEC for packet traffic. Specifically, they examine the tradeoff between the cost of increased bandwidth consumed by the FEC code versus the gain in packet error rate both through simulation and simple analytical models. The paper presents new analyses and results in two broad areas: i) the conditions under which FEC is effective in improving packer error rates, in terms of correlated cell loss levels for different packet sizes over different network extents, and ii) the cost-performance evaluation of using FEC in absolute terms that account for end-to-end delay, and the corresponding determination of the minimum physical network diameter over which FEC would be effective.

This paper introduces the concept of time slot synchronization in time-wave division multiplexed (TWDM) multihop lightwave networks. It is shown that the time slot assignments of the intermediate nodes in a multihop path have significant effect on the end-to-end message delay. This is different from traditional notions in routing, where the hop count and congestion control are the primary concerns. Assuming a TWDM embedding of a given logical topology already exists, we formulate the optimal routing problem for arbitrary propagation delays. We propose a graph unfolding technique which converts this problem into the shortest path routing problem for weighted graphs with well known solutions. We show a method to estimate the buffering cost at the intermediate nodes (in multihop routing) to accommodate high-bandwidth traffic (e.g., video). Next, we address the question: given a logical topology what should the TWDM embedding be so that the routing delays are optimized P This leads us to an iterative approach for TWDM embedding. Given an initial embedding an optimal route is estimated for each pair of nodes. A weighted average of these optimal route distances is used as a metric to evaluate the TWDM embedding. Using a heuristic the TWDM embedding is modified and the process iterated to improve along this metric. Preliminary performance results illustrating the improvement in routing delay are provided. For example, for a 4-cube network on average delay minimization of 10% to 20% is observed.

ATM has been widely accepted as the key enabling technology for emerging multimedia applications. We at the Honeywell Technology Center are investigating the application of this technology to real-time control systems. The Mercuri wide area ATM testbed is a collaborative research effort in this direction. In this paper we describe our experiences from a series of performance evaluation experiments on the Mercuri testbed. Besides measuring application level throughput and round-trip delay, we investigated the support for real-time provisions like priority and deadline guarantees, which are especially important for control applications. We also measured delay and jitter for remote video transfer under no-load and loaded conditions. The major conclusion of our experiments is that the end systems remain a major bottleneck for high speed communications. We point out possible causes of performance degradation in this paper and outline some issues that need to be resolved for ATM to become a viable alternative for real-time multimedia based control applications.

This paper describes the distributed system, network and software architecture, the application development environment, the performance, and the early lessons learned on the ATM LAN testbed Mercuri established at the Honeywell Technology Center, to develop distributed multimedia technologies for real-time control applications. We have developed a client-server-based software architecture on Sun Sparcstation-2s connected by a Fore Systems' ASX-100 ATM switch, with video processing handled by Parallax's X Video cards. The architecture enables network-transparent applications and provides simple primitives for multimedia capture, display, transmission, storage, and retrieval. A real-time multimedia-in-the-loop control application was developed as the vehicle for testing the capabilities and performance of the network. Our test measurements focus on the end-user-level performance metrics such as message throughput and round-trip delay as well as video-frame jitter under no-load and load conditions. Our results show that the maximum burst throughput that can be supported at the user level is 48 Mb/s using AAL 5, while round-trip delays for 4-kbyte messages are about 3 ms. Our experience reveals a number of performance bottlenecks and open issues in using commercial ATM switches for practical applications. Our conclusions are outlined.>

There is growing interest in using switched network technology such as asynchronous transfer mode (ATM) to support both continuous bit rate multimedia data and variable bit rate burst traffic for distributed computing. Most previous work and studies have focused only on the real-time support imposed by the isochronous requirements of the video or audio sources. This paper reports the results of our early study on how ATM can support real-time and prioritized traffic. We describe some basic approaches in handling real-time quality of service parameters within the context of ATM, and observe from simulation experiments that simple priority-based scheduling approaches at the virtual circuit level provides improvement in the deadline guarantee for all real-time traffic, especially the burst traffic. We believe that additional techniques such as deadline-based scheduling will be necessary to provide better real-time support.>

To address the growing demands of distributed computing, the authors propose a new switch architecture called VIPER+ that is based on a self-routing nonblocking network design. VIPER+ can be designed from simple 2*2 switching elements, either electrical or photonic. The self-routing properties of the switch enable scalability with the technology of the switching devices employed. The switch architecture, targeted for optical implementation, relies on simpledistributed routing algorithms and uses cut-through switching to avoid buffering at the switch interface. The authors outline the switch architecture using VIPER+, and the projected performance based on analytical modeling.>

Feedback shift registers (FSRs) are sometimes implemented with inversions between stages to improve their testability and their ability to locate faults. These intrainverted FSRs (IFSRs) can be realized with less overhead than standard linear feedback shift registers (LFSRs). It is shown how to relate the cyclic behavior of the LFSR and the corresponding IFSR, based on the same feedback polynomial, so that IFSRs can be designed to exploit the inherent implementation advantages while exhibiting the well-known behavior of LFSRs. In particular, it is shown that the cyclic and serial output behavior of LFSRs can be emulated by IFSRs when loaded with the appropriate initial states for most feedback shift register lengths and feedback polynomials. How the initial state for the IFSR can be derived, given the feedback polynomial and the initial state of the desired cycle in the LFSR, is described. Conditions under which such mapping of behavior cannot be guaranteed are given.>

This paper analyzes potential optical architectures for AI applications (such as knowledge-based systems). Our goal was to investigate architectures most suitable for implementation completely in optics. While optical computing appears to hold much promise because of its inherent parallelism and speed, constructing a symbolic processor or even a general purpose computer in optics requires examining many issues never before addressed. This paper presents these issues and discusses those architectures which appear most feasible in optics. We take into account fundamental physical limitations as well as the state-of-the-art optical device research. We conclude that, unlike in electronics, large-grained parallelism is not suitable for implementation in optics. We also find that functional languages, rather than logic languages, are better candidates for optics. Finally, we show that implementing an optical symbolic processor warrants the need for a real, or at least an emulated, addressable memory in optics.