Demo Data from EDBT 2026 / reviewers in the wild / expert
Edward Rutledge
dblp:33/5812
· DBLP profile ↗
2ranked-venue papers
1as first author
0since 2021 · last 2005
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1 · 1 first-authorApplied, interdisciplinary, general and emerging computing · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
High-performance computing · 44% Parallel and multicore computing · 44% Embedded and real-time systems · 13% |
Topics — the 3 heaviest of 3, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Parallel and multicore computing
parallel programming models |
0.1 | 1 | 2005 | Parallel VSIPL++: An Open Standard Software Library for High-Performance Parallel Signal Processing · Proc. IEEE 2005 |
High-performance computing › parallel numerical algorithms
parallel signal processing |
0.1 | 1 | 2005 | Parallel VSIPL++: An Open Standard Software Library for High-Performance Parallel Signal Processing · Proc. IEEE 2005 |
Embedded and real-time systems
real-time signal processing |
0.0 | 1 | 2005 | Parallel VSIPL++: An Open Standard Software Library for High-Performance Parallel Signal Processing · Proc. IEEE 2005 |
Methods — techniques the papers use, named apart from their topics
runtime optimization · 0.1offline mapping generation · 0.1adaptive optimization · 0.1
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2005 | Parallel VSIPL++: An Open Standard Software Library for High-Performance Parallel Signal ProcessingabstractReal-time signal processing consumes the majority of the world's computing power. Increasingly, programmable parallel processors are used to address a wide variety of signal processing applications (e.g., scientific, video, wireless, medical, communication, encoding, radar, sonar, and imaging). In programmable systems, the major challenge is no longer hardware but software. Specifically, the key technical hurdle lies in allowing the user to write programs at high level, while still achieving performance and preserving the portability of the code across parallel computing hardware platforms. The Parallel Vector, Signal, and Image Processing Library (Parallel VSIPL++) addresses this hurdle by providing high-level C++ array constructs, a simple mechanism for mapping data and functions onto parallel hardware, and a community-defined portable interface. This paper presents an overview of the Parallel VSIPL++ standard as well as a deeper description of the technical foundations and expected performance of the library. Parallel VSIPL++ supports adaptive optimization at many levels. The C++ arrays are designed to support automatic hardware specialization by the compiler. The computation objects (e.g., fast Fourier transforms) are built with explicit setup and run stages to allow for runtime optimization. Parallel arrays and functions in Parallel VSIPL++ also support explicit setup and run stages, which are used to accelerate communication operations. The parallel mapping mechanism provides an external interface that allows optimal mappings to be generated offline and read into the system at runtime. Finally, the standard has been developed in collaboration with high performance embedded computing vendors and is compatible with their proprietary approaches to achieving performance. James M. Lebak, Jeremy Kepner, Henry Hoffmann, Edward Rutledge |
Proc. IEEE | 4 |
| 2001 | PVL: An Object Oriented Software Library for Parallel Signal ProcessingabstractSummary form only given, as follows. The complete presentation was not made available for publication as part of the conference proceedings. Real-time signal processing consumes the majority of the world's computing power. Increasingly, programmable parallel microprocessors are used to address a wide variety of signal processing applications (e.g. scientific, video, wireless, medical, communication, encoding, radar, sonar and imaging). In programmable systems the major challenge is no longer hardware but software. Specifically, the key technical hurdle lies in mapping (i.e., placement and routing) of an algorithm onto a parallel computer in a general manner that preserves software portability. We have developed the Parallel Vector Library (PVL) to allow signal processing algorithms to be written using high level Matlab like constructs that are independent of the underlying parallel mapping. Programs written using PVL can be ported to a wide range of parallel computers without sacrificing performance. Furthemore, the mapping concepts in PVL provide the infrastructure for enabling new capabilities such as fault tolerance, dynamic scheduling and self-optimization. This presentation discusses PVL with particular emphasis on quantitative comparisons with standard parallel signal programming practices. Edward Rutledge, Jeremy Kepner |
CLUSTER | 1 |