Many signal and image processing applications impose a severe demand on the I/O bandwidth and computation power of general-purpose computers. The "systolic" concept offers guidelines in building cost-effective systems that balance I/O with computation. The resulting simplicity and regularity of such systems leads to modular designs suitable for VLSI implementation. We describe here a linear systolic array capable of evaluating a large class of inner-product functions used in signal and image processing. These include matrix multiplication, multidimensional convolutions using fixed or time-varying kernels, as well as various nonlinear functions of vectors. The system organization of a working prototype is also described.

A performance measure is derived for a multiclass hierarchical classifier under the assumption that a maximum likelihood rule is used at each node and the features at different nodes of the tree are class-conditionally statistically independent. The mean accuracy of an estimated hierarchical classifier is then defined as its performance averaged across all classification problems, when an estimated decision rule is used at every node. For a balanced binary decision tree, it is shown that there exists an optimum number of quantization levels for the features which maximizes the mean accuracy. The optimum quantization level increases with the number of training samples per class available to estimate the node decisions and is a nondecreasing function of the depth of the tree.