In the following we consider the action of the group of affine transformations on a class of patterns representable by continuous functions with compact support. It is first shown how to accomplish a reduction of the action of the affine group to that of the orthogonal group. In the two-dimensional case, it is shown how to find the particular orthogonal transformation necessary to complete a pattern match. Finally invariants under the orthogonal group are presented. Examples are given which present typical results obtained by implementing the techniques via a digital-optical scanner and minicomputer software.

A new network decomposition-optimization algorithm is presented and evaluated via computer simulation. The network is first partitioned into subnetworks on the basis of lines fitted via linear regression to the node locations weighted by their traffic loads. Each node is then connected via a data line of appropriate capacity to a concentrator-multiplexer. The concentrators are then regarded as nodes, and the process is repeated as often as required. The resulting singly connected network consists of a hierarchy of concentrators whose number, capacity, location, and interconnection are selected as an inherent part of the design procedure to minimize network cost. The linear regression clustering (LRC) design procedure is evaluated via computer simulation by comparing the costs and performance of the resulting networks with that which results from use of an algorithm based on the generally applicable network design approach of iterative local optimizations or "search" procedures. The data supplied to the LRC and search algorithms include randomly generated node locations and traffic matrices, and specific (realistic) cost vs. capacity schedules for data lines and concentrators. Comparisons of network costs, queuing and transmission delays, network reliability and network design costs show the LRC algorithm to be markedly superior to the search algorithm. The paper includes a brief discussion of our results, and their implications.

Cost-effective design of networks linking many remote terminals to a central computer (CPU) involves use of low-speed data lines to link geographically close terminals to concentrators. The concentrators are connected via high-speed data lines to the CPU. A design algorithm based on clustering of terminals followed by optimization of location, capacity and number of concentrators in each cluster is developed and evaluated. Evaluation is based on network designs for sets of 20 randomly (uniformly) generated locations of up to 500 terminals, with specific (realistic) cost versus capacity schedules being used for data lines and concentrators. In comparison with the popular Add algorithm, our linear regression clustering (LRC) algorithm has the following advantages: 1) the total cost of the concentrators, low-speed terminal lines, and high-speed CPU lines is typically 8 percent less; 2) the average transmission time delay at the terminals is typically 40 percent less; 3) the cost of adding low-speed data lines to connect additional terminals to concentrators in existing networks is typically 50 percent less; 4) the computational cost of design is typically 20 times less for 100-terminal networks and 150 times less for 500-terminals networks. Implications of the results and suggestions for further work are discussed.

A fast low-cost programmable optical-digital scanner-processor designed mainly for the purposes of edge and curve detection and on-line processing is presented. The main components of this system are a minicomputer, a linear photodiode array with driver and conversion interface, and a digital flatbed plotter.

A nonlinear picture-to-picture transformation is introduced and compared with a straightforward linear transformation. The criterion for comparison is based on the desire to smooth noisy or textured regions while retaining edge definition. Selected examples from a large number of simulations are presented. The transformation presented is believed to be superior to many techniques presently being employed.

In earlier papers no analysis characterizing faulty four-phase MOS logic arrays due to single load and sampling transistor faults has been given. In this note the models due to faulty load and sampling transistors are analyzed and discussed. Some useful results leading to faster simulation of four-phase MOS logic arrays with single faulty load and sampling transistors are presented. The computer simulation run time is reduced by one half for single-load transistor faults. At the end of each bit a shorted sampling transistor does not introduce any error for gate types 2 and 3 when initialization is with phase-4 time and for gate types 1 and 4 when initialization is with phase-2 time.