This report explores the critical field of plant disease recognition through the use of various machine learning algorithms. As agriculture faces increasing challenges from pathogens and diseases, the rapid and accurate identification of plant afflictions is essential for effective crop management and improved yields. We analyzed a range of machine learning techniques, from traditional classifiers to advanced deep learning models, focusing on their ability to classify and diagnose plant diseases using symptomatology and image analysis. Our study evaluates the strengths and limitations of these approaches, providing insights into their technical details and practical applicability in agriculture. Through comprehensive experimentation and performance comparisons, we highlight the efficacy and robustness of different algorithms in plant disease management. The findings offer valuable guidance on how these methodologies can contribute to agricultural sustainability, helping stakeholders refine disease management strategies, optimize resources, and enhance resilience against environmental and pathogenic challenges. In summary, this report underscores the potential of diverse machine learning algorithms in advancing plant disease recognition, aiming to support effective and sustainable agricultural practices.

Diabetic retinopathy (DR), a leading cause of vision loss among individuals with diabetes, necessitates accurate and timely diagnosis for effective management. This paper evaluates two classification models: the gray-level co-occurrence matrix (GLCM) and the convolutional neural network (CNN) ResNet-50 architecture, for automated DR diagnosis. The study employs retinal images from Kaggle and Zenodo datasets, assesses model performance, and optimizes the ResNet-50 parameters to enhance classification accuracy. The results demonstrate the superior performance of ResNet-50 compared to GLCM. The achieved accuracies for distinguishing normal and diabetic retinal images are $\mathbf{9 7. 8 8 9 \%}$ and $\mathbf{9 2. 0 5 3} \%$, based on Kaggle and Zenodo datasets, respectively. This indicates a robust performance of ResNet- 50 in multi-class classification tasks and highlights its potential for improving DR diagnosis systems. These findings underscore the significance of advanced computational techniques in early DR detection, offering enhanced diagnostic efficiency and potentially alleviating healthcare burdens.

In recent years, the proliferation of data and sensor measurements in various scientific fields, particularly within the realm of the Internet of Things, has opened new avenues for knowledge extraction through advanced data analysis techniques. However, the presence of outliers and anomalies poses significant challenges, leading to inaccuracies that can compromise analytical outcomes. Outliers are defined as data points that deviate markedly from other observations, often resulting from measurement errors or inconsistencies within the dataset. Their detection and removal during the data cleaning process are crucial for enhancing data quality and ensuring robust analysis. This study systematically investigates the impact of outliers and their detection on the accuracy and performance of various machine learning algorithms and statistical models in regression and classification tasks. A series of MATLAB simulations is conducted on standard datasets to evaluate the effects of outliers and validate the performance of different methodologies. The findings highlight the critical importance of effective outlier detection, demonstrating a marked improvement in the accuracy and reliability of analytical results.

Sleep Apnea is a serious sleep disorder that causes pauses in breathing during sleep. Breathing pauses can last from 10 seconds to several minutes and occur at least five times per hour. Sleep apnea may be diagnosed and monitored by In-Lab sleep study that requires the patient to stay overnight at the hospital. Even though an In-Lab polysomnography is very effective, it is highly costly. This paper presents a design to a user-friendly system that detects and monitors sleep apnea at home with a low cost. The device uses a nasal temperature sensor that senses the change in breathing to detect sleep apnea events. In case of a severe apnea event, the device can wake the patient up and send an SMS to an authorized person. Users can visualize the results of their sleep study using a mobile application. The application allows the user to send the recorded data to the doctor or the sleep center.

In this paper, we proposed four different machine learning classification models, i.e., Logistic Regression, Decision Tree, Multilayer Perceptron, and XGBoost, to predict Blood Pressure levels. Moreover, various performance metrics for each model have been calculated, such as accuracy, specificity, precision, recall, and F1 score. According to the findings and comparison of each classification model, XG-Boost achieves the highest classification accuracy of 90%. In contrast, Multilayer Perceptron, Decision Tree, and Logistic Regression achieved 87.33%, 83.83%, and 73.50% for blood pressure classifications, respectively. This study can forecast blood pressure-related diseases in the medical field.

High blood pressure (BP) or hypertension is a dangerous and deadly condition which can lead to serious disorders and high risk of heart attacks, strokes or death. Therefore, studying and monitoring blood pressure levels is highly important. In this study, we propose four distinct machine learning classification models to predict blood pressure levels. The classifiers used are: Random Forest (RF), CatBoost (CB), Support Vector Machine (SVM), and, K-Nearest Neighbors (KNN). Furthermore, several performance indicators such as accuracy, specificity, precision, recall, and F1 score have been calculated for each model. An accuracy of up to 90% was achieved for CATBoost and RF, and up to 87% and 78.33% for SVM and KNN respectively. This study was able to predict blood pressure-related disorders and cardiovascular diseases.

Electroencephalography (EEG) is a valuable instrument for acquiring brain signals from the scalp surface area that correlate to many states, one of which is epilepsy, which is defined as a central nervous system disorder that generates periods of abnormal brain activity, often known as seizures. Based on the EEG signal, frequencies are ranging from 0.1 Hz to more than 100 Hz, these signals are classified as delta, theta, alpha, beta, and gamma. This paper uses the four features extracted from EEG signal to detect Epileptic Seizures, by using a combination of both Discrete Wavelet Transform (DWT) and Artificial Neural Network (ANN) mainly using MATLAB. Bonn University EEG database has been used. The data was obtained using 128 channels and is divided into five different data classes: Z, N, O, F, and S. Each dataset class contains 100 segments taken from individual channels with a period of 23.6 seconds, or in other words, each dataset class contains 4097 pulses/samples with a sampling frequency of 173.61 Hz. Important statistical features were computed such as mean, standard deviation, skewness, and kurtosis. In this work only the gamma-band of the decomposed signal is used to extract the four statistical features, two classifiers are applied one to detect epilepsy and one to detect the seizure. the epilepsy classifier is 90.3 % accurate and the seizure classifier is 98.7% accurate.

Reliability has become one of the most vital requirements in wireless sensor networks (WSNs). One efficient way to increase the reliability is by using erasure coding techniques such as Reed-Solomon/Cauchy Reed-Solomon. The problem is the time required for encoding and decoding the data words, especially when large amount of data need to be sent like in complex WSN applications. In this paper, we propose HSC, a high-speed coding technique for reliable data transmission and we show that it reduces the number of XORs required for encoding by more than 94% (and consequently the encoding time) in comparison to the number of XORs required by Cauchy Reed-Solomon encoding. In addition, we present a new transmission scheme that works along with HSC to add redundancy on any size of a data load.

Many database applications, such as sequence comparing, sequence searching, and sequence matching, etc, process large database sequences. we introduce a novel and efficient technique to improve the performance of database applications by using a Hybrid GPU/CPU platform. In particular, our technique solves the problem of the low efficiency resulting from running short-length sequences in a database on a GPU. To verify our technique, we applied it to the widely used Smith-Waterman algorithm. The experimental results show that our Hybrid GPU/CPU technique improves the average performance by a factor of 2.2, and improves the peak performance by a factor of 2.8 when compared to earlier implementations.

The size of embedded software is increasing at a rapid pace. It is often challenging and time consuming to fit an amount of required software functionality within a given hardware resource budget. Code compression is a means to alleviate the problem by providing substantial savings in terms of code size. In this article we introduce a novel and efficient hardware-supported compression technique that is based on Huffman Coding. Our technique reduces the size of the generated decoding table, which takes a large portion of the memory. It combines our previous techniques, Instruction Splitting Technique and Instruction Re-encoding Technique into new one called Combined Compression Technique to improve the final compression ratio by taking advantage of both previous techniques. The instruction Splitting Technique is instruction set architecture (ISA)-independent. It splits the instructions into portions of varying size (called patterns) before Huffman coding is applied. This technique improves the final compression ratio by more than 20% compared to other known schemes based on Huffman Coding. The average compression ratios achieved using this technique are 48% and 50% for ARM and MIPS, respectively. The Instruction Re-encoding Technique is ISA-dependent. It investigates the benefits of reencoding unused bits (we call them reencodable bits) in the instruction format for a specific application to improve the compression ratio. Reencoding those bits can reduce the size of decoding tables by up to 40%. Using this technique, we improve the final compression ratios in comparison to the first technique to 46% and 45% for ARM and MIPS, respectively (including all overhead that incurs). The Combined Compression Technique improves the compression ratio to 45% and 42% for ARM and MIPS, respectively. In our compression technique, we have conducted evaluations using a representative set of applications and we have applied each technique to two major embedded processor architectures, namely ARM and MIPS.

Compressing program code compiled for VLIW processors to reduce the amount of memory is a necessary means to decrease costs. The main disadvantage of any code compression technique is the system performance penalty because of the extra time required to decode the compressed instructions during run time. In this paper we improve the performance of decoding compressed instructions by using our novel compression technique (LICT: Left-uncompressed Instruction Technique) which can be used in conjunction with any compression algorithm. Furthermore, we adapt a new code compression approach called Burrows-Wheeler (BW) [9] which has been used before in data compression. It significantly reduces the code size compared to state-of-the-art approaches for VLIW processors. Using our LICT in conjunction with the BW algorithm improves the performance explicitly (2.5x) with little impact on the compression ratio (only 3% compression ratio loss).

Reducing the code size of embedded applications is one of the important constraint in embedded system design. Code compression can provide substantial savings in terms of size. In this paper, we introduce a novel and efficient hardware-supported approach. Our approach investigates the benefits of re-encoding the unused bits (we call them re-encodable bits) in the instruction format for a specific application to improve the compression ratio. Re-encoding those bits may reduce the size of decoding table by more than 37%. We achieve compression ratios as low as 44% (including all overhead that incurs). We have conducted evaluations using a representative set of applications and have applied it to two major embedded processors, namely MIPS and ARM.

VLIW processors provide higher performance and better efficiency etc. than RISC processors in specific domains like multimedia applications etc. A disadvantage is the bloated code size of the compiled application code. Therefore, reducing the application code size is a design key issue for VLIW processors. In this paper we adapt a hardware-supported approach called ldquoDeflaterdquo which has been used before in data compression. It can significantly reduce the code size compared to state-of-the-art approaches for VLIW processors as we will show within this work. In fact, we enhance the ldquoDeflaterdquo algorithm by using a new technique called Filled Buffer Technique which can be applied to any Lempel-Ziv family algorithms to improve compression ratio in average by more than 13% compared to the sole ldquoDeflaterdquo algorithm. Using our Filled Buffer Technique in conjunction with ldquoV2Frdquo improves the compression ratio by 10%. We have conducted evaluations using a representative set of benchmarks (from Mediabench and Mibench) and have applied our scheme to two VLIW processors, namely TMS320C62x and TMS320C64x. We achieved allover compression ratios as low as 44% using the ldquoDeflaterdquo algorithm (61% and 56% in average for TMS320C62x and TMS320C64x, respectively).

Code density is of increasing concern in embedded system design since it reduces the need for the scarce resource memory and also implicitly improves further important design parameters like power consumption and performance. In this paper we introduce a novel, hardware-supported approach. Besides the code, also thelookuptables(LUTs) are compressed, that can become significant in size if the application is large and/or high compression is desired. Our scheme optimizes the number and size of generated LUTs to improve the compression ratio. To show the efficiency of our approach, we apply it to two compression schemes: ldquodictionary-basedrdquo and ldquostatisticalrdquo. We achieve an average compression ratio of 48% (already including the overhead of the LUTs). Thereby, our scheme is orthogonal to approaches that take particularities of a certain instruction set architecture into account. We have conducted evaluations using a representative set of applications and have applied it to three major embedded processor architectures, namely ARM, MIPS, and PowerPC.

The size of embedded software is rising at a rapid pace. It is often challenging and time consuming to fit an amount of required software functionality within a given hardware resource budget. Code compression is a means to alleviate the problem. In this paper we introduce a novel and efficient hardware-supported approach. Our scheme reduces the size of the generated decoding table by splitting instructions into portions of varying size (called patterns) before Huffman Coding compression is applied. It improves the final compression ratio (including all overhead that incurs) by more than 20% compared to known schemes based on Huffman Coding. We achieve allover compression ratios as low as 44%. Thereby, our scheme is orthogonal to approaches that take particularities of a certain instruction set architectures into account. We have conducted evaluations using a representative set of applications and have applied it to two major embedded processors, namely ARM and MIPS.

Code density is a major requirement in embedded system design since it not only reduces the need for the scarce resource memory but also implicitly improves further important design parameters like power consumption and performance. Within this paper we introduce a novel and efficient hardware-supported approach that belongs to the group of statistical compression schemes as it is based on canonical Huffman coding. In particular, our scheme is the first to also compress the necessary Look-up Tables that can become significant in size if the application is large and/or high compression is desired. Our scheme optimizes the number of generated look-up tables to improve the compression ratio. In average, we achieve compression ratios as low as 49% (already including the overhead of the lookup tables). Thereby, our scheme is entirely orthogonal to approaches that take particularities of a certain instruction set architecture into account. We have conducted evaluations using a representative set of applications and have applied it to three major embedded processor architectures, namely ARM, MIPS and PowerPC

The presented work uses code compression to improve the design efficiency of an embedded system. In particular, we present a method and architecture for compressing the so-called Look-up Tables that are necessary for the de-compression process. No other work has yet focused on minimizing the Look-up Tables that, as we show, have a significant impact on the total overhead of a hardware-based decompression scheme. We introduce a novel and very efficient hardware-supported approach based on Canonical Huffman Coding. Using the Lin-Kernighan algorithm we reduce the Look-up Table size by up to 45%. As a result, we achieve all-over compression ratios as low as 45% (already including the overhead of the Look-up Tables). Thereby, our scheme is entirely orthogonal to approaches that take particularities of a certain instruction set architecture into account, meaning that compression could be further improved. Factoring in the orthogonality, our scheme is the basis for not-yet-achieved efficiency in hardware-supported compression schemes. We have conducted evaluations using a representative set (in terms of size and application domain) of applications and have applied it to three major embedded processor architectures, namely ARM, MIPS and PowerPC. The hardware evaluation shows no performance penalty.