A deep neural network (DNN) system typically needs dynamic random access memories (DRAMs) for the data buffering. In this paper, an error-correction-code (ECC)-based technique is proposed to reduce the refresh power of DRAMs in the DNN system by extending the refresh period. By taking advantage of the characteristics of weight data of DNNs, a hybrid voting and ECC (VECC) method is used to protect the weight data from data retention fault caused by the refresh period extension. Analysis results show that the VECC method can achieve about 93% refresh power saving with about 0.5% accuracy loss and smaller than 0.5% check bit overhead on AlexNet, ResNet, and VGG19 convolutional neural network CNN models trained by ImageNet data set.

Various multi-channel dynamic random access memories (MC-DRAMs) have been proposed for the demand of high bandwidth. In this paper, we propose a channel-sharable built-in self-test (BIST) scheme for MC-DRAMs. The BIST can apply test patterns and evaluate test responses for multiple channels simultaneously regardless of the difference of the read/write latency among the channels. Therefore, the proposed BIST can reduce the test time. In our simulation cases show that the proposed BIST scheme can achieve about 11% test time reduction in comparison with an existing conventional shared BIST scheme for a two-channel 1G-bit DRAM by consuming about 0.003% additional area cost.

Neural network (NN) has been considered as an important factor for the success of many AI applications. As the von Neumann architecture is inefficient for NN computation, researchers have been investigating new semiconductor devices and architectures for neuromorphic computing. The crossbar RRAM, which is an emerging non-volatile memory composed of memristor devices, can be used to accelerate or emulate the NN computation. However, the memristor device defects exposed during manufacturing or field use may cause performance degradation in the NN, causing reliability issues to the neuromorphic hardware. In this paper, we consider two existing fault models for the 1T1R RRAM cell, i.e., the stuck-at fault and transistor stuck-on fault. Evaluation of their influence to the NN shows that for about 10% faulty cells in the memristor array, the accuracy for the MLP model degrades about 10%, and that for the LeNet 300-100 and LeNet 5 degrades by more than 65%. Therefore, we propose a self-healing and an error correction approach to reduce the accuracy degradation, and improve the reliability (lifetime) of the neuromorphic hardware. Our simulation results show that if we limit the accuracy degradation to within 5%, then the proposed error correction approach for the MLP model will be able to tolerate up to 40% faulty cells, and even up to 60% faulty cells for LeNet 300-100 and LetNet 5 models. Also, the error correction method can extend the lifetime of the neuromorphic hardware by 5% or more.

Three dimensional IC (3DIC) is becoming practical in today's consumer electronics designs. However, one major problem remains in design synthesis and flow: how to model heterogeneous die(s) with major logic die for power synthesis and signoff. This work provides a realistic model and principle for heterogeneous dies power network for 3DICs. It is based on given abstract or early stage information like bump location and power consumption from the provider. Our work also uses this model to synthesize power network with bottom logic die in the design flow. The result is DRC clean power network without IR and EM violation for all power domains. First, we analyze the location and power consumption of power bump for heterogeneous die(s). Second, according to previous analysis, we decide the stripe location and power sink location of heterogeneous dies model by a clustering method. After the initial model is synthesized, we convert it to a node graph with corresponding resistance of via and metal layer, also nodal voltages. Third, the model is optimized by using Sequential Linear Programming (SLP) to adjust stripe width. It will improve the model iteratively until the target IR-Drop is met. Furthermore, our work will create a pseudo DEF of the proposed model to be incorporated with the commercial tool for verification. We experiment on a real case from design house containing a 3D DRAM stack to demonstrate the effectiveness of this cross-layer realization. Results show that we can save 34% metal layer usage in one of the power domains in our case by using proposed methodology.

For a multi-die IC, the chip-level clock synchronization problem that aims to establish a global clock signal across multiple functional dies is harder to achieve than its single-die counterpart. In this work, we investigate a process resilient solution for this problem by incorporating Delay-Locked Loops (DLLs). The basic idea is to insert a DLL (which can be generated by a DLL compiler) in each functional die so that the clock latency (from a clock source to the clock ports of a number of FFs) in different dies can be dynamically tuned and equalized. This method has a benefit that the clock network of each die can be designed independently, while the clock skew of the entire chip can still be minimized at run-time, in response to its operating environment. In a preliminary study, experimental results on a pseudo 4-die design demonstrates how the clock skew as high as 233ps initially can be reduced to 34ps after the application of the proposed method.

Dynamic random access memory (DRAM) is one key component in modern electronic systems. In this paper, we propose a software-hardware-cooperated built-in self-test (SHC-BIST) scheme for the channel-based DRAMs. The testing of DRAMs consists of two major phases: DRAM initialization and DRAM array testing. Typically, the DRAM initialization process is short and executed in the beginning of the DRAM array testing. Thus, it is inefficient to realize it using the dedicated BIST hardware. On the other hand, it is not time efficient if we use the processor (software) to execute the DRAM array testing. Therefore, the SHC-BIST scheme uses a programmable BIST circuit to execute the DRAM array testing and takes advantage of the processor to execute the DRAM initialization and control the programmable BIST circuit such that the test time and hardware cost can be minimized. We verify the SHC-BIST scheme using a system with a LEON3 processor and a multi-channel DRAM.

Memristor is a resistive device which is considered as an alternative non-volatile device for future non-volatile memories. For a memristor memory, a reference current is needed for discriminating the high-resistance (ROFF) state from low-resistance (RON) state. The reference current has an impact on the yield and reliability of the memristor memory. In this paper, we propose a test method in associate with a current comparing circuit for finding the boundary currents of ROFF and RON states. Therefore, the user can set a good reference current according to the boundary currents. Simulation results show that if our test method is used to identify the boundary currents, 2.05% and 3.68% memristor cells which may be read incorrectly due to process variation for ROFF/RON = 50 and 3 can be eliminated, respectively.

With the shrinking of technology node, the data retention time of DRAM (DRAM) cells is widespread. Thus, the number of the cells with data retention faults is increased. In this paper, therefore, we propose a built-in self-repair (BISR) scheme for DRAMs using redundancies with physical and logical reconfiguration mechanisms. Spare rows and columns with physical reconfiguration mechanism are used to repair functional faults caused by defects. Spare bits with logical reconfiguration mechanism are used to replace data retention faults caused by process variation. Also, a diagnosis algorithm is proposed to identify data retention faults. Simulation results show that the proposed BISR scheme for a DRAM with 2 spare rows, 2 spare columns, and 8 spare bits can provide higher repair yield than a BISR scheme for a DRAM with 3 spare rows and 3 spare columns.

Three-dimensional (3-D) integration using through-silicon-via (TSV) is an emerging technology for integrated circuit (IC) design. It has been used in DRAM die stacking extensively. However, yield remains a key issue for volume production of 3-D RAMs. In this paper, we present a point-to-point interconnection structure derived from bus and propose a fault tolerance interface scheme for TSVs and micro bumps to enhance their manufacturing yield in the 3-D RAMs. The interconnection structure is inherently redundant and thus can replace defective TSVs or micro bumps without using repair circuits. Global and local reconfiguration approaches are proposed which benefit distinct situations of the 3-D RAM. Analyses show that the proposed intra-channel reconfigurable interconnection scheme can improve the yield of the 3-D RAM effectively. Compared to the previous solution using an inter-channel reconfigurable interconnection scheme, the yield improvement can be as large as 23% which is very significant.

Three-dimensional dynamic random access memory (3D DRAM) using through-silicon via (TSV) has been acknowledged as one good approach for overcoming the memory wall. However, the IO-channel power of a TSV-based 3D DRAM represents a significant portion of the 3D DRAM power. In this paper, we propose a built-in self-test (BIST) -assisted tuning scheme to adjust the driving capability of programmable drivers to fit the number of stacked 3D DRAM dies such that the IO-channel power can be minimized. A BIST design supporting specific test patterns and test flow for the driver tuning is proposed as well. Simulation results show that about 6.16×10 -- 2 J energy saving can be achieved for a logic-DRAM stack with 150fF/die TSV load under 100s write operations if the proposed BIST-assisted tuning scheme is implemented in the logic die.

3-D integration has been touted as an approach to reducing the lengths of critical paths in field-programmable gate arrays (FPGAs). A 3-D chip stacks a number of 2-D FPGA bare dies, interconnected by through-silicon vias (TSVs) and micro bumps, to attain a high packing density. However, the technology also introduces new types of defects, such as TSV void and microbump misalignment. Testing the interconnection faults becomes inevitable. In this paper, we present an automatic test pattern generator for open, short, and delay faults on 3-D FPGA interconnects by exploiting the regularity of switch matrix topology and forming repetitive paths with finite steps and with loop-back. The experimental results show that 12 test patterns (TPs) suffice to achieve 100% open fault coverage (FC). To detect all possible neighboring short faults, we need more than 40 TPs, whose number increases only slightly with the height of the 3-D FPGA. The TPs have high delay FC (96%) for 3-D FPGAs with the number of configurable logic blocks ranging from 50 × 50 × 2 to 50 × 50 × 6, demonstrating the scalability of our method.

This work presents an iterative look-up table based thermal simulator, I-LUTSim, to efficiently estimate the temperature profile of three-dimensional integrated circuits. I-LUTSim includes two stages. First, the pre-process stage constructs thermal impulse response tables. Then, the simulation stage iteratively calculates the temperature profile via the table lookup. With this two-stage scheme, the maximum absolute error of I-LUTSim is less than 0.41% compared with that of a commercial tool ANSYS. Moreover, I-LUTSim is at least an order of magnitude faster than a fast matrix solver SuperLU [1] for the full-chip temperature simulation.

Dynamic random access memory (DRAM) is one key component in handheld devices. It typically consumes significant portion of the energy of the device even if the device is in standby mode due to the refresh requirement. This paper proposes a hybrid error-correcting code (ECC) and redundancy (HEAR) technique to reduce the refresh power of DRAMs in standby mode. The HEAR circuit consists of a Bose-Chaudhuri-Hocquenghem (BCH) module and an error-bit repair (EBR) module to raise the error correction capability and minimize the adverse effects caused by the ECC technique such that the refresh period can be effectively prolonged and considerable refresh power reduction can be achieved. Analysis results show that the proposed HEAR scheme can achieve 40~70% of energy saving for a 2Gb DDR3 DRAM in standby mode. The area cost of parity data and ECC circuit of HEAR scheme is only about 63 % and 53 % of that of the ECC-only, respectively.

A parametric delay fault could arise in a through-silicon via (TSV) of a 3-D IC due to a manufacturing defect. Identification of such a fault is essential for fault diagnosis, yield-learning, and/or reliability screening. In this paper, we present an innovative design-for-testability technique called variable output thresholding. We discovered that by dynamically switching the output of a TSV from a normal inverter to a Schmitt-Trigger inverter, the parametric delay fault on the TSV can be characterized and detected. SPICE simulation reveals that this technique remains effective even when there is significant process variation. A scalable test infrastructure indicates that the test time is modest at only 17.2 ms for 1024 TSVs and 648.8 ms for 32768 TSVs when the test clock is running at 10 MHz.

In this paper, we propose a method and the required architecture for characterizing the propagation delays of the through Silicon vias (TSVs) in a 3-D IC. First of all, every two TSVs are paired up to form an oscillation ring with some peripheral circuits. Their joint performance can thus be measured roughly by the oscillation period of the ring. Next, we utilize a technique called sensitivity analysis to further derive the propagation delay of each individual TSV participating in an oscillation ring-a distilling process. In this process, we perturb the strength of the two TSV drivers, and then measure their effects in terms of the change of the oscillation ring's period. By some following analysis, the propagation delay of each TSV can be revealed. On top of scheme, we also present an architecture that can activate the performance characterization process of each test unit - that consists of two TSVs - one at a time in a proper sequence. The area overhead is only 18.97 equivalent two-input NAND gate per TSV, by which one can gain the ability to profile the capacitances and the propagation delays of the TSVs on a 3-D IC.

In this work, we present a robust small delay test scheme for through-silicon vias (TSVs) in a 3D IC. By changing the output inverter's threshold of a TSV in a testable oscillation ring structure, we can approximate the propagation delay across that TSV, and thereby detecting a small delay fault. SPICE simulation reveals that this Variable Output Thresholding (VOT) technique is still effective even when there is significant process variation in detecting a slow TSV with some resistive open defect that may escape the traditional at-speed test.

Three-dimensional (3D) random access memory (RAM) using through-silicon vias for inter-die interconnects has been considered as a new approach to overcome the memory wall. In this paper, we propose a built-in self-test (BIST) scheme for 3D RAMs. In the BIST scheme, a clock-domain-crossing-aware test pattern generator is proposed to cope with the clock-domain-crossing issue. An inter-die synchronization mechanism is also proposed to synchronize the BIST circuits in different dies. Furthermore, the BIST circuit provides the high-programmability feature to support the selection of RAMs in a die for testing such that it can support thermal management during the test. We design the proposed BIST scheme in a 3D IC with processor and RAM dies. Experimental results show that the area cost of the BIST circuit is very small. The area overhead of the BIST circuit for four 8192×64-bit RAMs in a die is only 0.45% using TSMC 90nm 1P9M CMOS process technology.

Capacitor mismatch is the linearity limiter of charge redistribution SAR ADCs. This paper aims at detecting and removing the mismatch induced missing-decision levels (MDLs), i.e., large positive DNLs; these errors lead to information loss that cannot be recovered by external calibration. A switched-capacitor based approach is proposed to avoid DC currents and reduce design overhead; the hardware modification also supports comparator offset compensation to improve calibration quality. Simulation results show that the proposed technique effectively improves the SAR ADC linearity in the presence of capacitor mismatch and comparator offset.

This paper presents a self-testing and calibration method for the embedded successive approximation register (SAR) analog-to-digital converter (ADC). We first propose a low cost design-for-test (DfT) technique which tests a SAR ADC by characterizing its digital-to-analog converter (DAC) capacitor array. Utilizing DAC major carrier transition testing, the required analog measurement range is just 4 LSBs; this significantly lowers the test circuitry complexity. Then, we develop a fully-digital missing code calibration technique that utilizes the proposed testing scheme to collect the required calibration information. Simulation results are presented to validate the proposed technique.

This paper presents a low-cost pre- and post-bond self-testing and calibration methodology for the successive approximation register (SAR) analog-to-digital converter (ADC) array in a three-dimensional (3-D) CMOS imager. The basic idea is to test and calibrate the SAR ADC by measuring the major carrier transitions (MCTs) of the internal digital-to-analog converter (DAC) capacitor array. During the pre-bond stage, when access to the die is very limited, we propose a calibration-oriented testing technique that only determines whether the ADC array can achieve the desired performance after calibration. This substantially reduces the required design-for-test (DfT) circuitry complexity and test time. Then, during the post-bond stage, more thorough characterization on the ADC array is performed, we utilize digital resources from the image signal processor (ISP) die to analyze the measurement results, compute the calibration parameters, and perform the digital calibration. Simulation results are presented to validate the proposed techniques.

Three-dimensional (3D) integration using through silicon via (TSV) has been widely acknowledged as one future integrated-circuit (IC) technology. A 3D IC including multiple dies connected with TSVs offers many benefits over current 2D ICs. However, the testing of 3D ICs is much more difficult than that of 2D ICs. In this paper, we propose a cost-effective built-in self-test circuit (BIST) to test TSVs of a 3D IC. The BIST scheme, arranging the TSVs into arrays similar to memory, has the features of low test/diagnosis time and low silicon area cost. Simulation results show that the area overhead of the BIST circuit implemented with 0.18μm CMOS technology for a 16×32 TSV array in which each TSV cell size is 45μm2is 2.24%. Also, the BIST needs only 130 clock cycles to test the TSV array with stuck-at faults. In comparison with the IEEE 1500-based test approach, the BIST scheme can achieve 85.2% area cost and 93.6% test time reduction.

3-D integration provides a means to overcome the difficulties in design and manufacturing of system-on-chip (SOC) and memory products. Introducing a short vertical interconnect, called through-silicon via (TSV), makes it feasible to repair and recycle bad dies by stacking. We propose a method to accomplish this using a dual-TSV hardwired switch (DTHS) in which the via-hole location is programmable. With the DTHS, we activate a spare and establish inter-die routing. The spare is nothing but a good part in another bad die. To be 3-D reparable, the design is partitioned into disjoint parts. The effort for the modification is minor in view of that a typical SOC is readily composed of modules with predefined functions and supply voltages. The DTHS is used: 1) to shut off power connections of both failed and unused parts; 2) to disconnect their signal paths; and 3) to redirect them to the selected good parts in the stacked dies. Despite the speed is degraded due to the extra load incurred by the DTHS, our simulation shows that the increase in delay time can be limited below 100 ps with an over-designed buffer which occupies 0.8% of the area of a 30 μm TSV, using a 65-nm CMOS process. The performance degradation turns out to be a necessary evil, since the increased height of the die stack leads to a thermal conductivity poorer than its 2-D counterpart. The 3-D patch die helps to shorten time-to-market and turn the irreparable dies profitable.

Next-decade computing power and interconnect bottle-neck challenge conventional IC design due to the ever increasing demands for high frequency and great bandwidth. Three-dimensional large-scale integration (3D-LSI) provides an opportunity to realize such high performance cores while reducing long latency. In this paper, we present a reference flow for the implementation of 3D via-last ICs in scalable face-to-back bonding style which leverages a mature set of 2D IC physical design tools. The first enabling technology of 3D-LSI is through-silicon via (TSV). Two kinds of TSV diameters are exemplified in the flow, namely, 5¿m and 50¿m. We propose an easy-to-adopt method to address the TSV-aware mixed-sized placement by considering the obstructions generated from adjacent-tier's floorplan, subject to certain TSV alignment constraints. Furthermore, the technique of clock tree synthesis (CTS) for a homogeneous die stack is developed to dramatically reduce the clock latency and skew. The mixed-sized placement and CTS of each tier can be done without iteration. To the best of our knowledge, no work has ever been published in literature discussing CTS for 3D via-last integration in a face-to-back fashion. Finally, to complete the proposed flow 2D timing-driven routing and modified off-line design rule check (DRC) and layout versus schematic (LVS) verification are performed very well.

The three-dimensional (3D) integration technology using through silicon via (TSV) provides many benefits over the 2D integration technology. Although many different manufacturing technologies for 3D integrated circuits (ICs) have been presented, some challenges should be overcome before the volume production of 3D ICs. One of the challenges is the testing of 3D ICs. This paper proposes test integration interfaces for controlling the design-for-test circuits in the dies of a 3D IC. The test integration interfaces can support the pre-bond, known-good stack, and post-bond tests. The minimum number of required test pads of the proposed test interface for pre-bond test using is only four. Furthermore, the test interface is compatible with the IEEE 1149.1 standard for the board-level testing. Simulation results show that the area overhead of the proposed test interfaces for a 3D IC with two dies in which each die implements the function of ITC'99 b19 benchmark is only about 0.15%.

In this paper, we propose a method that can characterize the propagation delays across the Through Silicon Vias (TSVs) in a 3D IC. We adopt the concept of the oscillation test, in which two TSVs are connected with some peripheral circuit to form an oscillation ring. Upon this foundation, we propose a technique called sensitivity analysis to further derive the propagation delay of each individual TSV participating in the oscillation ring-a distilling process. In this process, we perturb the strength of the two TSV drivers, and then measure their effects in terms of the change of the oscillation ring's period. By some following analysis, the propagation delay of each TSV can be revealed. Monte-Carlo analysis of a typical TSV with 30% process variation on transistors shows that the characterization error of this method is only 2.1% with the standard deviation of 8.1%.

Flash memories are a type of nonvolatile memory based on floating-gate transistors. The use of commodity and embedded flash memories is growing rapidly as we enter the system-on-chip era. Conventional tests for flash memories are usually ad hoc-the test procedure is developed for a specific design. As there is a large number of possible failure modes for flash memories, long test algorithms on complicated automatic test equipment (ATE) are commonly seen. The long test time results in high test cost. We propose a systematic approach in testing flash memories, including the development of March-like test algorithms, cost-effective fault diagnosis methodology, and built-in self-test (BIST) scheme. The improved March-like test algorithms can detect disturb faults-derived from the IEEE STD 1005-and conventional faults. As the memory array architecture and/or cell structure varies, the targeted fault set may change. We have developed a flash-memory fault simulator called RAMSES-FT, with which we can easily analyze and verify the coverage of targeted faults under any given test algorithm. In addition, the RAM test algorithm generator-test algorithm generator by simulation-has been enhanced based on RAMSES-FT, so that one can easily generate tests for flash memories, whether they are bit- or word-oriented. The proposed fault diagnosis methodology helps improve the production yield. We also develop a built-in self-diagnosis (BISD) scheme-a BIST design with diagnosis support. The BISD circuit collects useful test information for off-chip diagnostic analysis. It has unique test mode control that reduces test time and diagnostic data shift-out cycles by a parallel shift-out mechanism

Fault analysis is an important step in establishing detailed fault models or subsequent diagnostics and debugging of a semiconductor memory product. We have performed defect injection in the memory cell array of an industrial SRAM circuit and analyzed the faulty behavior with respect to each defect injected. We found that although some of the defects can be mapped to existing fault models, there are many defects that result in unmodeled faults. Moreover, a defect may exhibit a different faulty behavior at a different location in the cell array. The voltage and temperature parameters can also change the faulty behavior. The simulation results show that almost all open and short defects lead to stuck-at faults, transition faults, and data retention faults.

Failure analysis (FA) and diagnosis of memory cores plays a key role in system-on-chip (SOC) product development and yield ramp-up. Conventional FA based on bitmaps and the experiences of the FA engineer is time consuming and error prone. The increasing time-to-volume pressure on semiconductor products calls for new development flow that enables the product to reach a profitable yield level as soon as possible. Demand in methodologies that allow FA automation thus increases rapidly in recent years. This paper proposes a systematic diagnosis approach based on failure patterns and functional fault models of semiconductor memories. By circuit-level simulation and analysis, we have also developed a fault pattern generator. Defect diagnosis and FA can be performed automatically by using the fault patterns, reducing the time in yield improvement. The main contribution of the paper is thus a methodology and procedure for accelerating FA and yield optimization for semiconductor memories.

In this paper, we discuss a design-for-test technique for the detection of cell stability in static random access memory (SRAM). The power supply to the memory array is isolated and independently accessible from an external terminal. By lowering the array supply voltage, the cell stability is degraded, making the defective cells susceptible to noises induced by read/write operations. On-silicon characterization result using 0.18 /spl mu/m CMOS technology is reported. It shows that the weak tailing bits in the statistical distribution can manifest themselves. The implementation of the test mode is inherently low-cost and can be combined with previously proposed methods for an improved detection capability.

This paper deals with the problem of general modular multiplication, i.e., A/spl times/B mod M. To solve it in hardware, we suggest a simple lookup-table based approach and use the novel block multiplier which we have developed earlier on. The area (A) and time (T) complexities of this multiplier are both O(n log n) if carry-lookahead adders are used. Most previously proposed modular multipliers have put restriction on the ranges of the multiplicand A, the multiplier B, and the modulus M. Our modular multiplier is general, which releases the restriction on those operands.>