For a multichannel bio-potential signal acquisition front-end, it's total CMRR (TCMRR) is restricted by these three factors: the inherent CMRR (ICMRR) of the amplifier used in the acquisition front-end, the impedance mismatch of electrodes, and the systematic mismatch due to the shared reference electrode. This paper presents a 8-channel bio-potential front-end with multi-channel common-mode replication(MC-CMR). The frontend has been implemented in a standard CMOS 0.18-$\mu$m process, and the measurement results show that the amplifier has an adjustable gain of 46 to 64 dB, the input reference noise within 1Hz to 1k Hz is 1.62$\mu \mathrm{V}_{\mathrm{r}\mathrm{m}\mathrm{s}}$, TCMRR of the front-end is 100dB (at 50Hz). A single channel consumes 1.86$\mu$A at 1. 8V supply voltage, and the NEF is 2.7.

A Ku-band phased-array transceiver using 0.13- μm SiGe BiCMOS technology is proposed in this paper for satellite communication applications. With a 6-bit inductive compensated attenuator and a 6-bit phase shifter integrated in the common-leg of the receive (RX) and transmit (TX) paths, the transceiver realizes 6-bit phase and attenuation control of the RF signal. The transceiver realizes larger than 20 dB gain, with RMS gain/phase error less than 1 dB/10° within 16-18 GHz. The whole transceiver occupies 2.7 × 2.5 mm2chip area.

This paper presents a sampling speed-enhancement technique for SAR ADCs under near-threshold supply voltages. The proposed level-shifted boosting circuit generates sharp falling edges for the sampling clock, which is found a key factor limiting the sample speed under ultra-low voltages. A 0.35V 8b 12MS/s SAR ADC is designed in a 65nm CMOS technology to prove this technique. The post-layout simulated SAR ADC consumes only 6.71/iW and achieves SNDR of 48.8dB at Nyquist input, resulting in a figure-of-merit (FoM) of 2.47 fj/convertion-step. Simulation results show the proposed speed-enhancement technique improve the sampling rate of SAR ADC significantly under near-threshold supply voltages.

Computation-in-memory (CIM) is a feasible method to overcome "Von-Neumann bottleneck" with high throughput and energy efficiency. In this paper, we proposed a 1Mb Multi-Level (MLC) NOR Flash based CIM (MLFlash- CIM) structure with 40nm technology node. A multi-bit readout circuit was proposed to realize adaptive quantization, which comprises a current interface circuit, a multi-level analog shift amplifier (AS-Amp) and an 8-bit SAR-ADC. When applied to a modified VGG-16 Network with 16 layers, the proposed MLFlash-CIM can achieve 92.73% inference accuracy under CIFAR-10 dataset. This CIM structure also achieved a peak throughput of 3.277 TOPS and an energy efficiency of 35.6 TOPS/W with 4-bit multiplication and accumulation (MAC) operations.