Nanotechnology promises to open up new ways of scaling CMOS circuits by introducing new materials. For example, a hybrid circuit of CMOS gates and carbon nano-tubes (CNT), NEMS relay logic and emerging memory devices have been proposed for future nano-scale Field Programmable Gate Arrays (FPGAs). Hybrid circuits for use as FPGA configurable logic blocks (CLBs) are often proposed in the form of crossbar array architecture. However, many of emerging devices, such as NEMS relays, are not two terminal devices and are thus difficult to be used in the crossbar. On the other hand diode-based logics that are two-terminal devices that can be used in the crossbars, lack signal gain and inversion capability, which makes logic implementation with them difficult. We present nano-magnet/CMOS hybrid circuit using Magnetic Coupled Spin-Torque Devices (MCSTDs) to solve the signal gain and signal level restoration problems, allowing a crossbar array layout to be used throughout the entire crossbar array architecture FPGA. MCSTD consists of two spin torque input devices at the perimeter of a larger output device that serve as biasing dots and manipulate the magnetic reversal energy barrier of the center spintorque device. MCSTDs can implement entire Boolean logic (NAND, NOR, XOR, XNOR and NOT) simply by changing the location of the input spin-torque device and the magnetic shape anisotropy of the center device. The unique features of this logic include: 1) nonvolatility, 2) electronic gain for fan-out and signal restoration and 3) fewer devices to realize most logic functions (i.e. a single MCSTD gate can realize the entire range of Boolean logic gates, while CMOS takes up to 4 (NAND, NOR) or 16 (XOR, XNOR) transistors). The combination of non-volatility and smaller device count leads to reduced circuit area and lower power consumption. Signal gain is achieved by using asymmetric device dimensions between input and output devices. Area and energy consumption calculation of FPGA Look-Up Table (LUT) are performed to demonstrate the merits of the presented Nano-magnetic/CMOS hybrid circuit compared to CMOS. The results show a 94% savings in area at comparable energy consumptions when compared with 32nm CMOS technology node.