Demo Data from EDBT 2026 / reviewers in the wild / expert
Ju Young Lee
dblp:33/8863
· DBLP profile ↗
2ranked-venue papers
0as first author
1since 2021 · last 2023
0000-0001-7548-2284ORCID · corroborated
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1 · 1 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Electronic design automation · 100% | |
| Interdisciplinary, comprehensive, and emerging computing
1 paper |
Bioinformatics and computational biology · 100% |
Topics — the 4 heaviest of 4, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation › hardware verification and test › design for testability
built-in self-test |
0.7 | 1 | 2023 | Integrated Test Module Design for Microfluidic Large-Scale Integration · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2023 |
Electronic design automation › hardware test
defect detection |
0.7 | 1 | 2023 | Integrated Test Module Design for Microfluidic Large-Scale Integration · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2023 |
Electronic design automation
hardware verification and test |
0.7 | 1 | 2023 | Integrated Test Module Design for Microfluidic Large-Scale Integration · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2023 |
Bioinformatics and computational biology
lab-on-a-chip |
0.2 | 1 | 2023 | Integrated Test Module Design for Microfluidic Large-Scale Integration · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2023 |
Methods — techniques the papers use, named apart from their topics
integrated test module · 1.3BIST · 1.3
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2023 | Integrated Test Module Design for Microfluidic Large-Scale IntegrationabstractMicrofluidic large-scale integration (mLSI) is a promising lab-on-a-chip platform for high-throughput bio-applications. Due to the high integration scale and the small feature size, control channels on mLSI chips are prone to blockage and leakage defects, which may lead to faulty behavior of valves and erroneous experimental results. Thus, mLSI chips need to be tested before usage. Current mLSI-tests are mostly performed in a straightforward way by testing each valve individually, which is very time consuming and error prone. As the integration scale of mLSI chips keeps increasing, there is a pressing demand for more efficient test approaches. This work proposes the first built-in-self-test (BIST) method for mLSI with an integrated test module design. Instead of testing individual valves, the proposed method directly tests the control channels and thus greatly improves the test efficiency. Only${}({n}/{2})$and$\lceil \log _{2}(n+1)\rceil $test operations are required to test the blockage and leakage defects, respectively, of$n$control channels. The proposed test module consumes moderate area overhead and the test method is easy to operate. Neither specialized software nor external pressure sensors are required for carrying out the tests. Experiments show that our test approach is sensitive enough to detect defects that have a feature size as small as 10$\mu \text{m}$and that are several centimeters away from the test module. Mengchu Li, Yushen Zhang, Ju Young Lee, Hudson Gasvoda, Ismail Emre Araci, Tsun-Ming Tseng, Ulf Schlichtmann |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 3 |
| 2010 | On the efficiency of persistent scheduling for non-periodic real-time services in IEEE 802.16e systemabstractIn order to reduce MAP overhead for periodic small-sized services such as voice over IP (VoIP) service, a persistent scheduling scheme has been proposed in IEEE 802.16e/m. Although this persistent scheduling scheme is designed for periodic services, we propose to adopt the persistent scheduling for non-periodic real-time services with small-sized packets by considering the advantage of MAP overhead reduction. Assuming Poisson packet arrivals which show a typical non-periodic property, we mathematically analyze the average delay performance and derive the optimal resource allocation period of the persistent scheduling with a given delay requirement. In this paper, we also compare the average occupied resources per frame between the persistent scheduling and the conventional scheduling both in downlink and uplink. Analysis and numerical results show that for the non-periodic services, the persistent scheduling shows more efficient resource usage than that of the conventional scheduling with a smaller packet size and higher modulation and coding scheme. Ju Young Lee, Dan Keun Sung |
PIMRC | 2 |