This article presents a 28/39 GHz dual-band multi-mode low-noise amplifier (LNA), supporting wideband, concurrent, and reconfigurable dual-band operation modes. The proposed LNA consists of a three-stage cascode amplifier topology. The first and second stage loads incorporate a multi-tap switchable inductor and a reconfigurable transformer-based dual-band network, respectively. The primary coil inductance of the switchable inductor can be tuned by controlling the voltage of the secondary coil switches. The proposed reconfigurable dual-band network, comprising a transformer-based high-orderLCnetwork, provides different frequency responses for wideband, concurrent and reconfigurable modes. To mitigate the losses introduced by the transformer and switch, a Colpitts-style negative resistance compensation network (NRCN) is utilized. Fabricated in a 40-nm CMOS process, the LNA achieves the following measured performance: in wideband mode, the peak gain is 19.6 dB with a 3-dB bandwidth of 24.5-42.9 GHz, 3.4 dB minimum noise figure (NF), -9.6 to -6.5 dBm output 1-dB compression point (OP1dB). In concurrent mode, the measured results show the peak gains of 24/23.2 dB, 3.2/3.6 dB minimum NF and -11.8 to -7.6/-6.9 to -5.5 dBm OP1dB with 3-dB bandwidths of 25-31.7/38.1-42.5 GHz. The measured peak gains are 23.5/22dB with 3.1/3.5 dB minimum NF, -8.4 to -6.9/-7.3 to -4.9 dBm OP1dB and 3-dB bandwidths of 25.6-33.8/35.3-43.5 GHz in reconfigurable mode. The LNA occupies a core area of 0.14 mm2and consumes 15.2 mW, 19 mW, and 15.2 mW in wideband, concurrent, and reconfigurable modes, respectively.

This paper presents a 6-bit bidirectional variable-gain vector-summing active phase shifter (BVG-AVSPS) in TSMC 65nm CMOS technology. The proposed BVG-AVSPS consists of a novel bidirectional quadrature generator, four dual-function bidirectional amplifiers and two input/output matching networks. The proposed hybrid-based quadrature generator achieves low orthogonal amplitude and phase mismatches over a wideband with bidirectionality. Dual-function bidirectional amplifiers are employed to achieve either vector modulation or gain control functions in different operational directions. To improve the phase shifting accuracy during gain tuning, compensation transistors are employed in the dual-function bidirectional amplifiers to minimize additional phase variation. The proposed input/output networks based on L-type coupled inductors ensure proper impedance matching for both input and output in TX and RX modes. For both TX and RX modes over 24 GHz~32 GHz, the measured RMS phase and gain errors are 1.25∘~2.4∘and 0.42 dB~0.56 dB throughout 12.3 dB gain tuning range, respectively. With the help of the compensation transistors, measured phase variation is less than ±2.1∘during output gain tuning. The core area of proposed BVG-AVSPS is 625 µm×355 µm.

This article presents a CMOS voltage-combined Doherty power amplifier (PA) based on a broadband compact load modulation network (LMN) for fifth-generation (5G) millimeter-wave (mm-wave) mobile communication applications. By analyzing the frequency response of different types of Doherty power combiner, a novel voltage-combined Doherty LMN with shorted TL and corresponding design procedure are proposed to achieve broadband power back-off (PBO) bandwidth and compact footprint. A compact quadrature hybrid coupler without lumped capacitor is also devised to generate wideband quadrature signals. To improve PBO efficiency, an envelope detector is adopted to produce adaptive DC bias for auxiliary path. For the proof of concept, a dual-driver Doherty PA is implemented in 65-nm bulk CMOS technology with a chip size of 0.42 mm2 including all pads. The PA achieves a 3-dB small-signal$S_{21}$bandwidth from 21.1 to 30.4 GHz and a 1-dB saturated output power ($P_{\text {sat}}$) bandwidth from 24 to 30 GHz. The measured$P_{\text {sat}}$, output 1-dB compression point ($OP_{\text {1dB}}$), peak power-added efficiency (PAE) and PAE at 6dB-PBO are 20.0 dBm, 19.1 dBm, 24.6% and 20.0% at 27 GHz, respectively. For modulation measurements, the proposed PA under 64-quadrature-amplitude-modulated (64-QAM) signal at a data rate of 0.6/2.4 Gb/s achieves average output power ($P_{\text {avg}}$) of 11.5/4.8 dBm and average drain efficiency of 14.1%/3.9% with −25/−24.5 dB of error vector magnitude (EVM) and −29/−25.6 dBc of adjacent channel leakage ratio (ACLR) at 28 GHz, respectively.

An odd-element half-wave-rectification superposition (OHS) technique is presented and verified for designing the high-multiplication factor frequency multipliers. The proposed OHS technique superposes N odd-element phase-shifted half-wave-rectification (HWR) fundamental signals ($f_{0}$) to extract the 2N-order harmonic (2N$f_{0}$) while canceling the fundamental ($f_{0}$) and the 2ndto (2N-1)th harmonics without extra filtering. Compared with the reported even-element half-wave-rectification superposition technique (EHS) technique, the proposed OHS technique can realize the same multiplication factor but requires only a half number of the input HWR signals. Thus, the proposed OHS technique can be applied to design the high-multiplication factor frequency multiplier that is difficult to be implemented using the reported EHS technique. To verify the validity of the proposed OHS technique, a differential$\times 6$frequency multiplier with the input frequency range of 5-7GHz and output frequency range of 30–42 GHz was implemented in 65 nm CMOS process. The experimental results indicate that the implemented$\times 6$frequency multiplier exhibits more than 23 dBc rejection to the fundamental and 2ndto 5thharmonics without the extra filter. The DC power consumption is 4.6 mW for the core circuit.

An simplified vector-sum phase shifter (VSPS) topology is proposed in this article. The proposed VSPS topology employs only one 90° coupler to perform as both an I/Q generator and a vector summer. Compared with the literaturally reported VSPS, the proposed VSPS features a simpler topology and improved noise figure (NF) performance. Moreover, active baluns based on the self-calibration technique are employed to provide antiphase signals and improve the gain performance of the VSPS. For demonstration, a 24–30-GHz VSPS based on the proposed topology is implemented in the 65-nm CMOS process, exhibiting 3.5° rms phase error and 0.9-dB rms gain error. The average gain of the implemented VSPS is as high as 9 dB at the central frequency of 27 GHz. The NF ranges from 4.8 to 9 dB from 24 to 30 GHz, and the core chip size is$0.36\times0.59$mm2.

A 9.8–30.1 GHz CMOS low-noise amplifier (LNA) with a 3.2-dB minimum noise figure (NF) is presented. At the architecture level, a topology based on common-gate (CG) cascading with a common-source (CS) amplifier is proposed for simultaneous wideband input matching and relatively high gain. At the circuit level, multiple techniques are proposed to improve LNA performance. First, in the CG stage, loading effect is properly used instead of the conventional feedback technique, to enable simultaneous impedance and noise matching. Second, based on in-depth theoretical analysis, the inductor- and transformer-based g m -boosting techniques are employed for the CG and CS stages, respectively, to enhance the gain and reduce power consumption. Third, the floating-body method, which was originally proposed to lower NF in CS amplifiers, is adopted in the CG stage to further reduce NF. Fabricated in a 65-nm CMOS technology, the LNA chip occupies an area of only 0.2 mm 2 and measures a maximum power gain of 10.9 dB with −3 dB bandwidth from 9.8 to 30.1 GHz. The NF exhibits a minimum value of 3.2 dB at 15 GHz and is below 5.7 dB across the entire bandwidth. The LNA consumes 15.6 mW from a 1.2-V supply.