This work presents an ultralow-voltage and ultralow-power current-mode delta-sigma modulator designed for biomedical applications. To implement both the integrator and quantizer of the modulator, a bulk-driven current conveyor circuit is introduced. By satisfying the Barkhausen criterion, the proposed modulator can intrinsically oscillate, producing a pulse-density modulated (PDM) output. This clock-less operation avoids conventional quantization noise associated with discrete-time sampling. The current-mode design not only provides improved matching properties and a wider bandwidth but also simplifies the implementation of passive components, resulting in a smaller silicon area compared to voltage-mode modulators—though this area efficiency is partly achieved using off-chip components. The circuit has been fabricated using standard TSMC 0.18-$\mu $m CMOS technology, occupying a silicon area of$226~\mu $m×$264~\mu $m. Despite consuming only 34 nW of power, experimental results demonstrate a signal-to-noise and distortion ratio of 57.1 dB, corresponding to an effective resolution of 9.2bits with a bandwidth of 81 Hz. Additionally, the use of the bulk-driven method achieves an input dynamic range of ±24nA under a supply voltage of 0.3 V.

This brief implements a highly efficient fully differential transconductance amplifier, based on several input-to-output paths. Some traditional techniques, such as positive feedback, nonlinear tail current sources, and current mirror-based paths, are combined to increase the transconductance, thus leading to larger dc gain and higher gain bandwidth (GBW) product. Two flipped voltage-follower (FVF) cells are employed as variable current sources to provide class-AB operation and adaptive biasing of all other drivers. The proposed structure includes several input-to-output paths that play the role of dynamic current boosters during the slewing phase, thus improving the slew rate (SR) performance. The circuit was fabricated in a TSMC 0.18-$\mu \text{m}$CMOS process with a silicon area of$54.5\times 30.1\,\,\mu \text{m}$. Experimental results show a GBW of 173.3 MHz, a dc gain of 72.7 dB, and an SR of 139.4 V/$\mu \text{s}$for a capacitive load of$2\times5$pF. The proposed circuit consumes 619$\mu \text{W}$of power, under a supply voltage of 1.8 V.

In this brief, two current generator circuits are used to design a self-biasing transconductance amplifier. The current generators are configured using two n-channel and p-channel cascode current mirrors by which a high input dynamic range is achieved. Since such a topology creates positive feedback, the transconductance of the circuit is also increased causing higher performance. To ensure the stability of the circuit, constant current sources can be paralleled with the current mirror topologies, which of course are implemented using input drivers. Therefore, two n-channel and p-channel input differential pairs are added to the current generator circuits by which not only a rail-to-rail operation is achieved but also the amplifier is stabilized. The proposed circuit was fabricated in the TSMC 0.18-$\mu \text{m}$CMOS process with a silicon area of$54.1\times 71\,\,\mu \text{m}$. Under a 1.8-V supply voltage, the experimental results showed a high input common-mode range (ICMR), while a gain bandwidth (GBW) of 83.9 MHz was measured for a capacitive load of$2\times6$pF. In addition, a dc gain and a slew rate (SR) of 68.4 dB and 71.7 V/$\mu \text{s}$, respectively, were achieved.

This article presents the experimental results for a multiple-input operational transconductance amplifier (MI-OTA). To achieve extended linearity under 0.5-V low voltage supply, the circuit employs three linearization techniques: the bulk-driven (BD), the source degeneration, and the input voltage attenuation created by the MI metal-oxide-semiconductor transistor technique (MI-MOST). Although the linearization techniques result in reduced dc gain, the self-cascode transistors are used to boost the gain of the MI-OTA. Furthermore, the MI-MOST simplifies the internal structure of the OTA and may reduce the complexity of the applications. The MI-OTA operates in the subthreshold region and offers tunability by a bias current in the nanoampere range. The circuit is capable to work with 0.5-V supply voltage while consuming 24.77 nW. The circuit was fabricated using the 0.18-$\mu \text{m}$Taiwan Semiconductor Manufacturing Company (TSMC) CMOS technology and it occupies a 0.01153-mm2 silicon area. Intensive simulation and experimental results confirm the benefits and robustness of the design.

In this article, a new solution for an ultralow-voltage (ULV) ultralow-power (ULP) operational transconductance amplifier (OTA) is presented. Thanks to the combination of a low-voltage bulk-driven nontailed differential stage with the multipath Miller zero compensation technique, a simple class AB power-efficient ULV structure has been obtained, which can operate from supply voltages less than the threshold voltages of the employed MOS transistors, while offering rail-to-rail input common-mode range at the same time. The proposed OTA was fabricated using the 180-nm CMOS process from Taiwan Semiconductor Manufacturing Company (TSMC) and can operate from VDD ranging from 0.3 to 0.5 V. The 0.3-V version dissipates only 12.6 nW of power while showing a 64.7-dB voltage gain at 1-Hz, 2.96-kHz gain-bandwidth product, and a 4.15-V/ms average slew-rate at 30-pF load capacitance. The measured results agree well with simulations.

A flux-controlled memristor emulator built with off-the-shelf electronic devices and based on a TiO2model is presented in this article. The circuit proposed in this article uses the current mode approach based analog building blocks such as a second-generation current conveyor (CCII) and an operational transconductance amplifier (OTA) as an active element with few passive elements. The circuit shows a clear fingerprint of an ideal memristor. The offered emulator circuit can be made to operate in incremental and decremental modes and functions well up to 26.3 MHz. Nonvolatility, Monte Carlo sampling, and corner analysis simulations are executed to verify the robustness of the circuit. The functional verification of the presented circuit is performed using the 0.18-μm CMOS parameter at a supply voltage of ±1.2 V. The experimental demonstration is carried out by making a prototype on a breadboard using ICs AD844AN and CA3080, which exhibits a good agreement with theoretical and simulation results. The layout of the circuit, which requires a total chip area of 75 × 70 μm2, is also created. Single/parallel combinations of a memristor, a high-pass filter, and a chaotic system are presented to demonstrate its application.

A new solution for an ultralow-voltage bulkdriven (BD) asynchronous delta-sigma modulator is described in this paper. While implemented in a standard 0.18-μm CMOS process from the Taiwan Semiconductor Manufacturing Company and supplied with VDD = 0.3 V, the circuit offers a 53.3-dB signal-to-noise and distortion ratio, which corresponds to 8.56-bit resolution. In addition, the total power consumption is 37 nW, the signal bandwidth is 62 Hz, and the resulting power efficiency is 0.79 pJ/conversion. The above-mentioned features have been achieved employing a highly linear transconductor and a hysteretic comparator based on nontailed BD differential pair.

The last few decades, a great deal of attention has been paid to low-voltage (LV) low-power (LP) integrated circuits design since the power consumption has become a critical issue. Among many techniques used for the design of LV LP analog circuits, the Bulk-driven principle offers a promising route towards this design for many aspects mainly the simplicity and using the conventional MOS technology to implement these designs. This paper is devoted to the Bulk-driven (BD) principle and utilizing this principle to design LV LP building blocks of Current Mirror (CM), Enhanced Current Mirror (ECM), Operational Transconductance Amplifier (OTA), Current Conveyor (CCII) and Current Differencing Transconductance Amplifier (CDTA) in standard CMOS processes and supply voltage ±0.7V. The simulation results have been carried out by the Spice simulator using the 0.25μ CMOS technology from TSMC.