Sample selection is a straightforward technique to combat noisy labels, aiming to prevent mislabeled samples from degrading the robustness of neural networks. However, existing methods mitigate compounding selection bias either by leveraging dual-network disagreement or additional forward propagations, leading to multiplied training overhead. To address this challenge, we introduce Jump-teaching, an efficient sample selection framework for debiased model update and simplified selection criterion. Based on a key observation that a neural network exhibits significant disagreement across different training iterations, Jump-teaching proposes a jump-manner model update strategy to enable self-correction of selection bias by harnessing temporal disagreement, eliminating the need for multi-network or multi-round training. Furthermore, we employ a sample-wise selection criterion building on the intra variance of a decomposed single loss for a fine-grained selection without relying on batch-wise ranking or dataset-wise modeling. Extensive experiments demonstrate that Jump-teaching outperforms state-of-the-art counterparts while achieving a nearly overhead-free selection procedure, which boosts training speed by up to 4.47× and reduces peak memory footprint by 54%.

Continual learning (CL) is a technique that enables neural networks to constantly adapt to their dynamic surroundings. Despite being overlooked for a long time, this technology can considerably address the customized needs of users in edge devices. Actually, most CL methods require huge resource consumption by the training behavior to acquire generalizability among all tasks for delaying forgetting regardless of edge scenarios. Therefore, this paper proposes a compact algorithm called LightCL, which evaluates and compresses the redundancy of already generalized components in structures of the neural network. Specifically, we consider two factors of generalizability, learning plasticity and memory stability, and design metrics of both to quantitatively assess generalizability of neural networks during CL. This evaluation shows that generalizability of different layers in a neural network exhibits a significant variation. Thus, we Maintain Generalizability by freezing generalized parts without the resource-intensive training process and Memorize Feature Patterns by stabilizing feature extracting of previous tasks to enhance generalizability for less-generalized parts with a little extra memory, which is far less than the reduction by freezing. Experiments illustrate that LightCL outperforms other state-of-the-art methods and reduces at most 6.16× memory footprint. We also verify the effectiveness of LightCL on the edge device.

In this paper, we propose a shared-memory parallel field-programmable gate array (FPGA) router called ParRA. Basically, ParRA is composed of hybrid partitioning and parallel routing. During the hybrid partitioning, first an FPGA is split into multiple subregions and nets are geographically partitioned into local subsets. As the intersubregion nets usually overlap each other, these nets cannot be routed in parallel. Second, the intersubregion nets are further partitioned into conflict-free subsets. Since each conflict-free subset consists of intersubregion nets do not overlap each other, the nets in the same conflict-free subset can be routed in parallel. In this way, we significantly increase the number of nets that have potential to be routed in parallel. During the parallel routing process, two novel parallel routing strategies are applied to route the nets in conflict-free and local subsets, respectively. With conflict-free subsets, sinks in the same conflict-free subset are routed in parallel while conflict-free subsets are routed one by one. On the contrast, local subsets are routed in parallel while the nets in the same local subset are routed sequentially. With the two different parallel routing strategies, we reduce the interference between threads and balance the workload of threads, which contributes to gain more parallelism. The proposed parallel router provides deterministic routing results. The experimental results show that ParRA achieves an average speedup of $24.3 {\times }$ with 16 threads compared to VPR 7.0, has no negative impact on the quality of results.

In this paper, we present a new field-programmable gate array (FPGA) routing approach on the basis of the PathFinder routing algorithm. During each routing iteration, our approach applies a novel timing-based rerouting strategy to only reroute the illegal paths. At a lower level, each maze expansion is started from the relatively close part of current routing tree to search for the target sink on the routing resource graph. Experimental results demonstrate that on average the proposed approach reduces the routing runtime by 68.5% compared with the timing-driven router in versatile place and route FPGA placement and routing framework, with reduction of 2.5% and 1.4% in critical path delay and wirelength, respectively.

Peer-to-Peer(P2P) reputation systems are essential to evaluate the trustworthiness of the nodes in a P2P system. This paper presents a distributed algorithm HP2PSORT based on SORT that enables a node to estimate the trustworthiness of other nodes based on the past interactions and recommendations. In an HP2P network, by using the filtering mechanism, the calculation method of the service trust and the dynamic calculation of the threshold value, we show that HP2PSORT outperforms SORT.

Recent research advocates performance heterogeneous multicore processors, where cores in the same processor have same instruction set architecture (ISA) but often different performance characteristics. These architectures are able to deliver higher performance per watt and area for programs with diverse architectural requirements than comparable homogeneous ones. However, such power and area efficiencies of performance heterogeneous multicore systems can only be accomplished when thread-to-core assignment is made according to the characteristics of both the workload and the core. In this paper, we propose a new metric, ASTPI (Average Stall Time Per Instruction), to measure the properties of threads. We design, implement and evaluate a new online monitoring approach called ESHMP, which is based on the metric. Our evaluation in the Linux 2.6.21 operating system shows that ESHMP delivers scalability while adapting to a wide variety of applications.

To deal with the model checking issue of rectangular hybrid systems, a constraint system called hybrid zone is introduced for the representation and manipulation of rectangular hybrid automata state-spaces. Model checking procedures for rectangular hybrid systems based on timed computation tree logic are given. The hybrid zone is proved to be closed to the operations required in these model checking procedures, which enables it to be used as the basis for the infinite state-space exploring of rectangular hybrid automata. To represent hybrid zones, a data structure difference constraint matrix is introduced.