An FPGA-based wired-logic CNN processor is presented that can process CIFAR-10 at 13.7μJ/prediction with an 88% accuracy, which is 2,036 times more energy-efficient than the prior state-of-the-art FPGA-based processor. Energy efficiency is greatly improved by implementing all processing elements and wirings in parallel on a single FPGA chip to eliminate the memory access. By utilizing both (1) a non-linear neural network which saves on neurons and synapses and (2) a shift register-based wired-logic architecture, hardware resource usage is reduced by three orders of magnitude.

A 5.3 times smaller and 2.6 times more energy-efficient all-digital wired-logic processor which infers MNIST with 90.6% accuracy and 1.2nJ of energy consumption has been developed. To improve area efficiency of wired-logic architecture, nonlinear neural network (NNN), which is a neuron and synapse efficient network, and logical compression technology to implement it with area-saving and low-power digital circuits by logic synthesis are proposed, and asynchronous digital combinational circuit DNN hardware has been developed.

A 0.13mJ/prediction with 68.6% accuracy single- chip wired-logic artificial intelligence (AI) processor is developed in a 16nm field-programmable gate array (FPGA). Compared with conventional von-Neumann architecture-based AI processors, the energy efficiency is greatly improved by eliminating the DRAM/BRAM access. A technical challenge of the conventional wired-logic processor is the large amount of hardware resources required. To implement a large convolutional neural network (CNN) into a single FPGA chip, two techniques are used: (1) a sparse neural network which is called non-linear neural network (NNN), and (2) a newly developed raster-scan-based wired-logic architecture. The amount of hardware resources required is reduced by a factor of 5.4. Compared with the state-of-the-art FPGA-based processor, 238 times better energy efficiency is achieved with the same accuracy on the CIFAR-I00 task. In addition, 7 times better energy efficiency is achieved compared with the state-of- the-art application-specific integrated circuit (ASIC) processor.

• In this study, we propose a 13.7mJ/prediction 88% accuracy CIFAR-10 single-chip wired-logic processor in 16-nm FPGA by utilizing a newly developed 98%-pruned ultra-sparse, binary-weight nonlinear neural network (NNN) and a shift-register based pipelined wired-logic architecture. Compared with the state-of-the-art FPGA-based processor, 2,036 times better energy efficiency is achieved.