The landscape of Verilog toolchains for electronic design automation (EDA) is diverse, and their reliability is crucial, as errors can lead to significant debugging challenges and delays in development. Methodologies such as testing and formal verification have been applied to identify and eliminate defects in these toolchains. We propose a framework named VeriXmith to interconnect design tools involved in logical synthesis and simulation for cross-checking. These tools process circuit designs and produce outputs in different languages, such as Verilog netlists from synthesizers and C++ programs from simulators. Since these outputs represent the same circuit semantics, we can leverage this semantic consistency to verify the tools that translate one representation into another. Our approach involves creating semantics extractors to extend the range of circuit representations available for semantic equivalence checking by converting them into a canonical and comparable form. Additionally, we develop mutation operators for Verilog designs to introduce new data/control paths and language constructs, enhancing the diversity of circuit designs as test inputs. By validating semantic equivalence, our framework successfully identifies defects in existing Verilog toolchains. An exploratory experiment uncovers 31 previously unknown bugs in well-known open-source Verilog tools, including Verilator and Yosys.

While research has shown that the agile chip design methodology is promising to sustain the scaling of computing performance in a more efficient way, it is still of limited usage in actual applications due to two major obstacles: 1) Lack of tool-chain and developing framework supporting agile chip design, especially for large-scale modern processors. 2) The conventional verification methods are less agile and become a major bottleneck of the entire process. To tackle both issues, we propose MINJIE, an open-source platform supporting agile processor development flow. MINJIE integrates a broad set of tools for logic design, functional verification, performance modelling, pre-silicon validation and debugging for better development efficiency of state-of-the-art processor designs. We demonstrate the usage and effectiveness of MINJIE by building two generations of an open-source superscalar out-of-order RISC-V processor code-named XIANGSHAN using agile methodologies. We quantify the performance of XIANGSHAN using SPEC CPU2006 benchmarks and demonstrate that XIANGSHAN achieves industry-competitive performance.

We analyze the outage performance of a lossy forwarding (LF) relaying system with the simultaneous wireless information and power transfer (SWIPT) capability. In the system of LF with SWIPT (LF-SWIPT), a source broadcasts its message to both a relay and a destination. A relay node with SWIPT functionality harvests energy and decodes information from the source signal. The energy is split into two parts for information processing and message forwarding, respectively. For information processing, the relay attempts to decode the incoming source signal and forms an estimate. Unlike the existing decode-and-forward SWIPT system (DF-SWIPT), the estimate is always forwarded using the harvested energy. The destination performs joint decoding to recover the message with the signals received from both the source node and the relay node. We derive the outage probability for the LF-SWIPT system based on the theorem ofsource coding with side information. The simulation results demonstrate that the proposed system achieves significant gains (around 1–2 dB) compared to the DF-SWIPT system. We further evaluate the impact of the distance and the power splitting (PS) strategy on the system performance using simulations. Finally, we build an optimization algorithm on the PS ratio by maximizing the admissible region from the theoretical perspective.